CAT5132ZI-00-GT3

CAT5132
http://onsemi.com
4
Table 7. A.C. CHARACTERISTICS
Symbol Parameter (see Figure 6)
V
CC
= 2.7 5.5 V
Units
Min Max
F
SCL
Clock Frequency 400 kHz
T
I
(Note 11) Noise Suppression Time Constant at SCL & SDA Inputs 50 ns
t
AA
SLC Low to SDA Data Out and ACK Out 1
ms
t
BUF
(Note 11) Time the bus must be free before a new transmission can start 1.2
ms
t
HD:STA
Start Condition Hold Time 0.6
ms
t
LOW
Clock Low Period 1.2
ms
t
HIGH
Clock High Period 0.6
ms
t
SU:STA
Start Condition Setup Time (for a Repeated Start Condition) 0.6
ms
t
HD:DAT
Data in Hold Time 0 ns
t
R
(Note 11) SDA and SCL Rise Time 0.3
ms
t
F
(Note 11) SDA and SCL Fall Time 300 ns
t
SU:STO
Stop Conditions Setup Time 0.6
ms
t
DH
Data Out Hold Time 100 ns
11. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. POWER UP TIMING (Notes 12, 13)
Symbol Parameter Min Max Units
t
PUR
Power-up to Read Operation 1 ms
t
PUW
Power-up to Write Operation 1 ms
Table 9. WIPER TIMING
Symbol Parameter Min Max Units
t
WRPO
Wiper Response Time After Power Supply Stable 5 10
ms
t
WRL
Wiper Response Time After Instruction Issued 5 10
ms
Table 10. WRITE CYCLE LIMITS
Symbol Parameter Min Max Units
t
WR
Write Cycle Time (see Figure 7) 5 ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
Table 11. RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Max Units
N
END
(Note 12) Endurance MILSTD883, Test Method 1033 100,000 Cycles
T
DR
(Note 12) Data Retention MILSTD883, Test Method 1008 100 Years
12.This parameter is tested initially and after a design or process change that affects the parameter.
13.t
PUR
and t
PUW
are the delays required from the time VCC is stable until the specified operation can be initiated.
CAT5132
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5
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 2. Resistance between R
W
and R
L
Figure 3. I
CC
2 (NV Write) vs. Temperature
TAP POSITION TEMPERATURE (C)
1129680644832160
0
2
4
6
8
10
12
11090703010103050
0
50
100
200
250
300
350
400
Figure 4. Absolute Linearity Error per Tap
Position
Figure 5. Relative Linearity Error
TAP POSITION TAP POSITION
1129680644832160
1.0
0.8
0.4
0.2
0.2
0.4
0.8
1.0
1129680644832160
0.5
0.4
0.2
0.1
0.1
0.2
0.4
0.5
R
WL
(KW)
I
CC
2 (mA)
A
LIN
ERROR (LSB)
A
LIN
ERROR (LSB)
128 50 130
150
V
CC
= 5.5 V
V
CC
= 2.7 V
128
0.6
0
0.6
T
amb
= 25C
R
total
= 10 K
128
T
amb
= 25C
R
total
= 10 K
0.3
0
0.3
V
CC
= 2.7 V; V+ = 8 V
V
CC
= 5.5 V; V+ = 16 V
V
CC
= 2.7 V; V+ = 8 V
V
CC
= 5.5 V; V+ = 16 V
V
CC
= 2.7 V; V+ = 8 V
V
CC
= 5.5 V; V+ = 16 V
CAT5132
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6
Figure 6. Bus Timing
Figure 7. Write Cycle Timing
SCL
SDA IN
SDA OUT
CONDITION
ADDRESS
ACK
SCL
SDA 8TH BIT
BYTE n
STOP
t
WR
CONDITION
START
t
BUF
t
SU:STO
t
SU:DAT
t
DH
t
R
t
LOW
t
LOW
t
HIGH
t
HD:DAT
t
AA
t
HD:STA
t
F
t
SU:STA

CAT5132ZI-00-GT3

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Digital Potentiometer ICs DPP 15V 128 taps I2C
Lifecycle:
New from this manufacturer.
Delivery:
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