CAT5132ZI-00-GT3 Datasheet CAT5132ZI-50-GT3, CAT5132ZI-10-GT3, CAT5132ZI-00-G | P7-P9

CAT5132

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SERIAL BUS PROTOCOL

The following defines the features of the I

C bus protocol:

1. Data transfer may be initiated only when the bus is

not busy.

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high

will be interpreted as a START or STOP condition.

The device controlling the transfer is a master, typically a

processor or controller, and the device being controlled is the

slave. The master will always initiate data transfers and

provide the clock for both transmit and receive operations.

Therefore, the CAT5132 will be considered a slave device

in all applications.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The CAT5132 monitors the SDA and

SCL lines and will not respond until this condition is met

(see Figure 8).

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition (see Figure 8).

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data (see Figure 9).

The CAT5132 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

responds with an acknowledge after receiving each 8-bit

byte.

When the CAT5132 is in a READ mode it transmits 8 bits

of data, releases the SDA line, and monitors the line for an

acknowledge. Once it receives this acknowledge, the

CAT5132 will continue to transmit data. If no acknowledge

is sent by the Master, the device terminates data transmission

and waits for a STOP condition.

Acknowledge Polling

The disabling of the inputs can be used to take advantage

of the typical write cycle time. Once the STOP condition is

issued to indicate the end of the write operation, the

CAT5132 initiates the internal write cycle. ACK polling can

be initiated immediately. This involves issuing the START

condition followed by the slave address. If the CAT5132 is

still busy with the write operation, no ACK will be returned.

If the CAT5132 has completed the write operation, an ACK

will be returned and the host can then proceed with the next

instruction operation.

Figure 8. Start/Stop Condition

SDA

SCL

START

CONDITION

STOP

CONDITION

Figure 9. Acknowledge Condition

START

SCL FROM

MASTER

ACK SETUP ( t

SU:DAT

)

BUS RELEASE DELAY (RECEIVER)

ACK DELAY ( t

)

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

BUS RELEASE DELAY (TRANSMITTER)

CAT5132

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DEVICE DESCRIPTION

Access Control Register

The volatile register WCR and the non-volatile register

DR are accessed only by addressing the volatile Access

C protocol for all read

and write operations (see Table 12). The first byte is the slave

address/instruction byte (see details below). The second

byte contains the address (02h) of the AR register. The data

in the third byte controls which register WCR (80h) or DR

(00h) is being addressed (see Figure 10).

Slave Address Instruction Byte Description

The first byte sent to the CAT5132 from the master

processor is called the Slave Address Byte. The most

significant five bits of the slave address are a device type

identifier. For the CAT5132 these bits are fixed at 01010

(refer to Table 13).

The next two bits, A1 and A0, are the internal slave

address and must match the physical device address which

is defined by the state of the A1 and A0 input pins. Only the

device with slave address matching the input byte will be

accessed by the master. This allows up to 4 devices to reside

on the same bus. The A1 and A0 inputs can be actively

driven by CMOS input signals or tied to V

or Ground.

The last bit is the READ/WRITE bit and determines the

function to be performed. If it is a “1” a read command is

initiated and if it is a “0” a write is initiated. For the AR

After the Master sends a START condition and the slave

address byte, the CAT5132 monitors the bus and responds

with an acknowledge when its address matches the

transmitted slave address.

Table 12. ACCESS CONTROL REGISTER

000000ST 11A00000010A ASP00000000

000000ST 11A00000010A ASP10000000

ACK

STOP

ACK

START

ID4

ID3

ID2

ID1

ID0

1st byte 2nd byte

AR address − 02h

3rd byte

WCR(80h) / DR(00h) selection

Table 13. BYTE 1 SLAVE ADDRESS AND INSTRUCTION BYTE

Device Type Identifier Slave Address

ID4

(MSB)

ID3

ID2

ID1

ID0

R/W

Read/Write

(LSB)

Figure 10. Access Register Addressing Using 3 Bytes

& INSTRUCTION

BUS ACTIVITY:

MASTER

SDA LINE

FIXED

VARIABLE

AR REGISTER

ADDRESS

SLAVE

WCR/DR

SELECTION

CAT5132

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Wiper Control Register (WCR) Description

The CAT5132 contains a 7-bit Wiper Control Register

which is decoded to select one of the 128 switches along its

resistor array. The WCR is a volatile register and is written

with the contents of the nonvolatile Data Register (DR) on

power-up. The Wiper Control Register loses its contents

when the CAT5132 is powered-down. The contents of the

WCR may be read or changed directly by the host using a

READ/WRITE command after addressing the WCR (see

Table 12 to access WCR). Since the CAT5132 will only

make use of the 7 LSB bits (The first data bit, or MSB, is

ignored) on write instructions and will always come back as

a “0” on read commands.

A write operation (see Table 14) requires a Start condition,

followed by a valid slave address byte, a valid address byte

00h, a data byte and a STOP condition. After each of the

three bytes the CAT5132 responds with an acknowledge. At

this time the data is written only to volatile registers, then the

device enters its standby state.

Table 14. WCR WRITE OPERATION

000000ST 11A00000010A ASP10000000

ACK

STOP

ACK

START

ID4

ID3

ID2

ID1

ID0

1st byte 2nd byte

AR address − 02h

3rd byte

WCR(80h) selection

000000ST 11A00000000A ASPxxxxxxxx

ACK

STOP

ACK

START

slave address byte WCR address − 00h data byte

An increment operation (see Table 15) requires a Start

condition, followed by a valid increment address byte

(01011), a valid address byte 00h. After each of the two

bytes, the CAT5132 responds with an acknowledge. At this

time if the data is high then the wiper is incremented or if the

data is low the wiper is decremented at each clock. Once the

stop is issued then the device enters its standby state with the

WCR data as being the last inc/dec position. Also, the wiper

position does not roll over but is limited to min and max

positions.

Table 15. WCR INCREMENT/DECREMENT OPERATION

000000ST 11A00000010A ASP10000000

ACK

STOP

ACK

START

ID4

ID3

ID2

ID1

ID0

1st byte 2nd byte

AR address − 02h

3rd byte

WCR(80h) selection

001000ST 11A00000000A SP11110000

STOP

ACK

START

slave address byte WCR address − 00h increment (1) / decrement (0) bits

A read operation (see Table 16) requires a Start condition,

followed by a valid slave address byte for write, a valid

address byte 00h, a second START and a second slave

address byte for read. After each of the three bytes, the

CAT5132 responds with an acknowledge and then the

device transmits the data byte. The master terminates the

read operation by issuing a STOP condition following the

last bit of Data byte.

Table 16. WCR READ OPERATION

000000ST 11A00000010A ASP10000000

ACK

STOP

ACK

START

ID4

ID3

ID2

ID1

ID0

1st byte 2nd byte

AR address − 02h

3rd byte

WCR(80h) selection

000000ST 11A00000000

ACK

START

slave address byte WCR address − 00h

000001ST 11A0XXXXXXXSP

STOP

START

slave address byte data byte

P1-P3 P4-P6 P7-P9 P10-P12

CAT5132ZI-00-GT3

Mfr. #:

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Manufacturer:

ON Semiconductor

Description:

Digital Potentiometer ICs DPP 15V 128 taps I2C

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CAT5132ZI-00-GT3

CAT5132ZI-00-GT3

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