SC16C554DIB64,157 Datasheet SC16C554DIA68,512, SC16C554DIA68,518, SC16C554DIA68,529 | P13-P15

Philips Semiconductors

SC16C554/554D

Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Product data Rev. 05 — 10 May 2004 13 of 55

9397 750 13132

6. Functional description

The SC16C554/554D provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data

stream into parallel data that is required with digital data systems. Synchronization for

the serial data stream is accomplished by adding start and stop bits to the transmit

data to form a data character. Data integrity is insured by attaching a parity bit to the

data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex,

especially when manufactured on a single integrated silicon chip. The

SC16C554/554D represents such an integration with greatly enhanced features. The

SC16C554/554D is fabricated with an advanced CMOS process to achieve low drain

power and high speed requirements.

The SC16C554/554D is an upward solution that provides 16 bytes of transmit and

receive FIFO memory, instead of none in the 16C454. The SC16C554/554D is

designed to work with high speed modems and shared network environments that

require fast data processing time. Increased performance is realized in the

SC16C554/554D by the larger transmit and receive FIFOs. This allows the external

processor to handle more networking tasks within a given time. In addition, the four

selectable levels of FIFO trigger interrupt and automatic hardware/software ﬂow

control is uniquely provided for maximum data throughput performance, especially

when operating in a multi-channel environment. The combination of the above greatly

reduces the bandwidth requirement of the external controlling CPU, increases

performance, and reduces power consumption.

The SC16C554/554DAI68 combines the package interface modes of the 16C454/554

and 68C454/554 series on a single integrated chip. The 16 mode interface is

designed to operate with the Intel-type of microprocessor bus, while the 68 mode is

intended to operate with Motorola and other popular microprocessors. Following a

reset, the SC16C554/554DAI68 is downward compatible with the 16C454/554 or the

68C454/554, dependent on the state of the interface mode selection pin, 16/68.

The SC16C554/554D is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and

up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the maximum

speed is 3 Mbit/s).

The rich feature set of the SC16C554/554D is available through internal registers.

Automatic hardware/software ﬂow control, selectable transmit and receive FIFO

trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface,

modem interface controls, and a sleep mode are all standard features. In the

16 mode, INTSEL and MCR[3] can be conﬁgured to provide a software controlled or

continuous interrupt capability. Due to pin limitations of the 64-pin package, this

feature is offered by two different LQFP64 packages. The SC16C554D operates in

the continuous interrupt enable mode by bonding INTSEL to V

internally. The

SC16C554 operates in conjunction with MCR[3] by bonding INTSEL to GND

internally.

Philips Semiconductors

SC16C554/554D

Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Product data Rev. 05 — 10 May 2004 14 of 55

9397 750 13132

6.1 Interface options

Two user interface modes are selectable for the PLCC68 package. These interface

modes are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature

corresponds to the early 16C454/554 and 68C454/554 package interfaces

respectively.

6.2 The 16 mode interface

The 16 mode conﬁgures the package interface pins for connection as a standard

16 series (Intel) device and operates similar to the standard CPU interface available

on the 16C454/554. In the 16 mode (pin 16/68 = logic 1), each UART is selected with

individual chip select (CSx) pins, as shown in Ta ble 3.

6.3 The 68 mode interface

The 68 mode conﬁgures the package interface pins for connection with Motorola, and

other popular microprocessor bus types. The interface operates similar to the

68C454/554. In this mode, the SC16C554/554D decodes two additional addresses,

A3-A4, to select one of the four UART ports. The A3-A4 address decode function is

used only when in the 68 mode (16/68 = logic 0), and is shown in Table 4.

Table 3: Serial port channel selection, 16 mode interface

CSA CSB CSC CSD UART channel

1111none

0111A

1011B

1101C

1110D

Table 4: Serial port channel selection, 68 mode interface

CS A4 A3 UART channel

1 n/a n/a none

000A

001B

010C

011D

Philips Semiconductors

SC16C554/554D

Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Product data Rev. 05 — 10 May 2004 15 of 55

9397 750 13132

6.4 Internal registers

The SC16C554/554D provides 17 internal registers for monitoring and control. These

registers are shown in Table 5. These registers function as data holding registers

(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register

(FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),

and a user accessible scratchpad register (SPR). Beyond the general 16C554

features and capabilities, the SC16C554/554D offers an enhanced feature register

set (EFR, Xon/Xoff1-2) that provides on-board hardware/software ﬂow control.

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

[3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to

‘BF’ (HEX).

6.5 FIFO operation

The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control

level, but not the transmit trigger level. The receiver FIFO section includes a time-out

function to ensure data is delivered to the external CPU. An interrupt is generated

whenever the Receive Holding Register (RHR) has not been read following the

loading of a character or the receive trigger level has not been reached.

Table 5: Internal registers decoding

A2 A1 A0 READ mode WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)

[1]

0 0 0 Receive Holding Register Transmit Holding Register

0 0 1 Interrupt Enable Register Interrupt Enable Register

0 1 0 Interrupt Status Register FIFO Control Register

0 1 1 Line Control Register Line Control Register

1 0 0 Modem Control Register Modem Control Register

1 0 1 Line Status Register n/a

1 1 0 Modem Status Register n/a

1 1 1 Scratchpad Register Scratchpad Register

Baud rate register set (DLL/DLM)

[2]

0 0 0 LSB of Divisor Latch LSB of Divisor Latch

0 0 1 MSB of Divisor Latch MSB of Divisor Latch

Enhanced register set (EFR, Xon/off 1-2)

[3]

0 1 0 Enhanced Feature Register Enhanced Feature Register

1 0 0 Xon1 word Xon1 word

1 0 1 Xon2 word Xon2 word

1 1 0 Xoff1 word Xoff1 word

1 1 1 Xoff2 word Xoff2 word

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P55

SC16C554DIB64,157

Mfr. #:

Buy SC16C554DIB64,157

Manufacturer:

NXP Semiconductors

Description:

IC UART QUAD 64LQFP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

SC16C554DIB64,157

SC16C554DIB64,157

Products related to this Datasheet