SC16C554DIB64,157 Datasheet SC16C554DIA68,512, SC16C554DIA68,518, SC16C554DIA68,529 | P25-P27

Philips Semiconductors

SC16C554/554D

Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Product data Rev. 05 — 10 May 2004 25 of 55

9397 750 13132

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive

FIFO trigger levels, and select the DMA mode.

7.3.1 DMA mode

Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or

receive operation, and is similar to the 16C454 mode. Transmit Ready (TXRDY) will

go to a logic 0 whenever an empty transmit space is available in the Transmit Holding

Holding Register (RHR) is loaded with a character.

Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The

transmit interrupt is set when there are one or more FIFO locations empty. The

receive interrupt is set when the receive FIFO ﬁlls to the programmed trigger level.

However, the FIFO continues to ﬁll regardless of the programmed level until the FIFO

is full. RXRDY remains a logic 0 as long as the FIFO ﬁll level is above the

programmed trigger level.

7.3.2 FIFO mode

Table 10: FIFO Control Register bits description

Bit Symbol Description

7:6 FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to

be loaded until it is full. Refer to Ta ble 1 1.

5:4 FCR[5:4] Not used; initialized to logic 0.

3 FCR[3] DMA mode select.

Logic 0 = Set DMA mode ‘0’ (normal default condition).

Logic 1 = Set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C554/554D is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode

(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are

no characters in the transmit FIFO or transmit holding register, the

TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a

logic 1 after the ﬁrst character is loaded into the transmit holding

Receive operation in mode ‘0’: When the SC16C554/554D is in

mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1;

FCR[3] = logic 0) and there is at least one character in the receive FIFO,

the

RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a

logic 1 when there are no more characters in the receiver.

Philips Semiconductors

SC16C554/554D

Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Product data Rev. 05 — 10 May 2004 26 of 55

9397 750 13132

Transmit operation in mode ‘1’: When the SC16C554/554D is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1), the

TXRDY pin will be a

logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one

or more FIFO locations are empty.

Receive operation in mode ‘1’: When the SC16C554/554D is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been

reached, or a Receive Time-Out has occurred, the

RXRDY pin will go to

a logic 0. Once activated, it will go to a logic 1 after there are no more

characters in the FIFO.

2 FCR[2] XMIT FIFO reset.

Logic 0 = No FIFO transmit reset (normal default condition).

Logic 1 = Clears the contents of the transmit FIFO and resets the

FIFO counter logic (the transmit shift register is not cleared or

altered). This bit will return to a logic 0 after clearing the FIFO.

1 FCR[1] RCVR FIFO reset.

Logic 0 = No FIFO receive reset (normal default condition).

Logic 1 = Clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

0 FCR[0] FIFO enable.

Logic 0 = Disable the transmit and receive FIFO (normal default

condition).

Logic 1 = Enable the transmit and receive FIFO. This bit must be a

‘1’ when other FCR bits are written to, or they will not be

programmed.

Table 11: RCVR trigger levels

FCR[7] FCR[6] RX FIFO trigger level

001

014

108

1114

Table 10: FIFO Control Register bits description

…continued

Bit Symbol Description

Philips Semiconductors

SC16C554/554D

Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Product data Rev. 05 — 10 May 2004 27 of 55

9397 750 13132

7.4 Interrupt Status Register (ISR)

The SC16C554/554D provides six levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with six

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged

until the pending interrupt is serviced. Whenever the interrupt status register is read,

the interrupt status is cleared. However, it should be noted that only the current

pending interrupt is cleared by the read. A lower level interrupt may be seen after

re-reading the interrupt status bits. Table 12 “Interrupt source” shows the data values

(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated

with each of these interrupt levels.

Table 12: Interrupt source

Priority

level

ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

1 000110LSR(Receiver Line Status

2 000100RXRDY (Received Data

Ready)

2 001100RXRDY (Receive Data

time-out)

3 000010TXRDY (Transmitter

Holding Register Empty)

4 000000MSR (Modem Status

5 010000RXRDY (Received Xoff

signal) / Special character

6 100000CTS, RTS change of state

Table 13: Interrupt Status Register bits description

Bit Symbol Description

7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFO is

not being used. They are set to a logic 1 when the FIFOs are

enabled.

Logic 0 or cleared = default condition.

5:4 ISR[5:4] INT priority bits 4-3. These bits are enabled when EFR[4] is set to

a logic 1. ISR[4] indicates that matching Xoff character(s) have

been detected. ISR[5] indicates that CTS, RTS have been

generated. Note that once set to a logic 1, the ISR[4] bit will stay a

logic 1 until Xon character(s) are received.

Logic 0 or cleared = default condition.

3:1 ISR[3:1] INT priority bits 2-0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Ta bl e 12).

Logic 0 or cleared = default condition.

0 ISR[0] INT status.

Logic 0 = An interrupt is pending and the ISR contents may be

used as a pointer to the appropriate interrupt service routine.

Logic 1 = No interrupt pending (normal default condition).

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SC16C554DIB64,157

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NXP Semiconductors

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IC UART QUAD 64LQFP

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SC16C554DIB64,157

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