Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data Rev. 05 — 10 May 2004 28 of 55
9397 750 13132
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 14: Line Control Register bits description
Bit Symbol Description
7 LCR[7] Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch and enhanced feature register enabled.
6 LCR[6] Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
5 LCR[5] Set parity. If the parity bit is enabled, LCR[5] selects the forced
parity format. Programs the parity conditions (see Table 1 5).
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a
logical 1 for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a
logical 0 for the transmit and receive data.
4 LCR[4] Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,
LCR[4] selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of
logic 1s in the transmitted data. The receiver must be
programmed to check the same format (normal default
condition).
Logic 1 = EVEN Parity is generated by forcing an even number
of logic 1s in the transmitted data. The receiver must be
programmed to check the same format.
3 LCR[3] Parity enable. Parity or no parity can be selected via this bit.
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during the transmission,
receiver checks the data and parity for transmission errors.
2 LCR[2] Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see Tabl e 16 ).
Logic 0 or cleared = default condition.
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Ta ble 1 7).
Logic 0 or cleared = default condition.
