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85102AGILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Low Skew, 1-to-2, Differential/LVCMOS-
to-0.7V HCSL Fanout Buffer
85102
DATA SHEET
85102 REVISION B DECEMBER 19, 2014 1 ©2014 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 85102I is a low skew, high performance 1-to-2 Differen-
tial-to-HCSL fanout buffer. The 85102I has a differential clock input.
The CLK0, nCLK0 input pair can accept most standard differential
input levels. The clock enable is internally synchronized to eliminate
runt clock pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the 85102I ideal for those applications demanding well defi ned
performance and repeatability.
FEATURES
• Two 0.7V differential HCSL outputs
• Selectable differential CLK0, nCLK0 or LVCMOS inputs
• CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
• CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 500MHz
• Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
• Output skew: 65ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Propagation delay: 3.2ns (maximum)
• Additive phase jitter, RMS: 0.14ps typical @ 250MHz
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM PIN ASSIGNMENT
85102I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm body package
G Package
Top View
Q0
nQ0
Q1
nQ1
CLK_EN
CLK_SEL
IREF
CLK1
CLK0
nCLK0
D
LE
Q
0
1
Pulldown
Pulldown
Pulldown
Pullup
Pullup/Pulldown
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK_EN
CLK_SEL
CLK0
nCLK0
CLK1
nc
nc
IREF
GND
V
DD
Q0
nQ0
Q1
nQ1
V
DD
VDD
Low Skew, 1-to-2, Differential/LVCMOS-to-0.7V HCSL
Fanout Buffer
85102 DATA SHEET
2 REVISION B 12/19/14
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
Number Name Type Description
1 CLK_EN Input Pullup
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high. LVTTL
/ LVCMOS interface levels.
2 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
3 CLK0 Input Pulldown Non-inverting differential clock input.
4 nCLK0 Input
Pullup/
Pulldown
Inverting differential clock input.
5 CLK1 Pulldown Single-ended clock input. LVTTL / LVCMOS interface levels.
6, 7 nc Unused No connect.
8 IREF Input
An external fi xed resistor (475Ω) from this pin to ground provides a refer-
ence current used for differential current-mode Qx/nQx clock outputs.
9, 10, 15 V
DD
Power Positive supply pins.
11, 12 nQ1, Q1 Output Differential output pair. HCSL interface levels.
13, 14 nQ0, Q0 Output Differential output pair. HCSL interface levels.
16 GND Power Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION B 12/19/14
85102 DATA SHEET
3 Low Skew, 1-to-2, Differential/LVCMOS-to-0.7V HCSL
Fanout Buffer
TABLE 3A. CONTROL INPUT FUNCTION TABLE
FIGURE 1. CLK_EN TIMING DIAGRAM
Inputs Outputs
CLK_EN CLK_SEL Selected Source Q0:Q1 nQ0:nQ1
0 0 CLK0, nCLK0 Disabled; LOW Disabled; HIGH
0 1 CLK1 Disabled; LOW Disabled; HIGH
1 0 CLK0, nCLK0 Enabled Enabled
1 1 CLK1 Enabled Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

85102AGILF

Mfr. #:
Buy 85102AGILF
Manufacturer:
IDT
Description:
Clock Buffer DIFFERENTIAL CLOCK
Lifecycle:
New from this manufacturer.
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