REVISION B 12/19/14
85102 DATA SHEET
9 Low Skew, 1-to-2, Differential/LVCMOS-to-0.7V HCSL
Fanout Buffer
APPLICATIONS INFORMATION
INPUTS:
CLK INPUT
For applications not requiring the use of a clock input, it can be left
fl oating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
CLK/nCLK I
NPUTS
For applications not requiring the use of the differential input, both
CLK and nCLK can be left fl oating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
LVCMOS C
ONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
DIFFERENTIAL OUTPUTs
All unused differential outputs can be left fl oating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left fl oating or terminated.
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage V
REF
= V
DD
/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help fi lter noise on the DC bias. This bias circuit should be located
as close to the input pin as possible. The ratio of R1 and R2 might
need to be adjusted to position the V
REF
in the center of the input
voltage swing. For example, if the input clock swing is 2.5V and V
DD
= 3.3V, R1 and R2 value should be adjusted to set V
REF
at 1.25V.
The values below are for when both the single-ended swing and V
DD
are at the same voltage. This confi guration requires that the sum of
the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the input will attenuate the signal in half. This can be
done in one of two ways. First, R3 and R4 in parallel should equal the
transmission line impedance. For most 50 applications, R3 and R4
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
can be 100Ω. The values of the resistors can be increased to reduce
the loading for slower and weaker LVCMOS driver. When using
single ended signaling, the noise rejection benefi ts of differential
signaling are reduced. Even though the differential input can handle
full rail LVCMOS signaling, it is recommended that the amplitude
be reduced. The datasheet specifi es a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
IL
cannot be less
than -0.3V and V
IH
cannot be more than V
DD
+ 0.3V. Though some of
the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifi cations are characterized and guaranteed by
using a differential signal.
