Si5110
4 Rev. 1.4
1. Detailed Block Diagram
Limiting
Amp
CDR
1:4
DE-
MUX
4:1
MUX
CMU
FIFO
8:4
MUX
8:4
MUX
RXDIN
SLICELVL
LTR
PHA S EA DJ
RXLOL
LOSLVL
LOS
TXDOUT
TXSQLCH
TXCLKOUT
TXLOL
REFRA TE
BWSEL[1:0]
REFSEL
LLBK
REFCLK
TXCLK4IN
TXCLK4OUT
TXDIN[3:0]
RXCLK2DIV
RXCLK2DSBL
RXCLK1DSBL
RXCLK2
RXCLK1
RXDOUT[3:0]
DLBK
RXSQLCH
TXCLKDSBL
SLICEMODE
RXA MPMON
RXMSBSEL
FIFOERR
FIFORST
TXMSBSEL
LPTM
LLBK
LOS
Si5110
Rev. 1.4 5
2. Electrical Specifications
Figure 1. Differential Voltage Measurement
(RXDIN, RXDOUT, RXCLK1, RXCLK2, TXDIN, TXDOUT, TXCLKOUT, TXCLK4OUT, TXCLK4IN)
Figure 2. Data to Clock Delay
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition
Min
*
Typ
Max
*
Unit
Ambient Temperature T
A
–20 25 85 °C
LVTTL I/O Supply Voltage V
DDIO
1.71 3.47 V
Si5110 Supply Voltage V
DD
1.71 1.8 1.89 V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
V
ISE
, V
OSE
V
ID
,V
OD
(V
ID
= 2 V
ISE
)
Differential
I/Os
Differential
Voltage Swing
Single Ended Voltage
Differential Peak-to-Peak Voltage
SIGNAL +
SIGNAL –
(SIGNAL+) – (SIGNAL–)
V
ICM
, V
OCM
V
t
V
I
0 V
V
TXDOUT,
TXDIN
TXCLKOUT,
TXCLK4IN
t
CP
t
CH
RXDOUT
RXCLK1
t
cq1
t
cq2
t
CD
Si5110
6 Rev. 1.4
Figure 3. I/O Rise/Fall Times
Table 2. DC Characteristics
(V
DD
= 1.8 V ±5%, T
A
= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Supply Current I
DD
Full Duplex 575 640 mA
Line/Diagnostic
Loopback
635 700 mA
Power Dissipation P
D
Full Duplex 1.0 1.2 W
Line/Diagnostic
Loopback
—1.11.3W
Voltage Reference (VREF) V
REF
VREF driving 10 kΩ
load
1.21 1.25 1.29 V
Common Mode Input Voltage
(RXDIN)
V
ICM
0.4 0.5 0.6 V
Differential Input Voltage Swing
(RXDIN)
(at bit error rate of 10
–12
)
V
ID
Figure 1 30 2000*
mV
PPD
Common Mode Output Voltage
(TXDOUT, TXCLKOUT)
V
OCM
0.7 0.9 1.1 V
Differential Output Voltage Swing
(TXDOUT, TXCLKOUT), Differen-
tial pk-pk
V
OD
Figure 1 1000 1200 1400
mV
PPD
LVPECL Input Common Mode
Voltage (REFCLK)
V
ICM
0.8 1.2 2.4 V
LVPECL Input Voltage Swing,
Differential pk-pk (REFCLK)
V
ID
Figure 1 250 2400
mV
PPD
LVPECL Input Limits V
LIMIT
0—2.5
V
LVDS Input Voltage Level
(TXDIN, TXCLK4IN)
V
I
0.8 1.2 2.4 V
LVDS Input Voltage, Differential
(TXDIN, TXCLK4IN)
V
ID
200
mV
PPD
LVDS Output Voltage Level
(RXDOUT, RXCLK1, RXCLK2,
TXCLK4OUT)
V
O
100 Ω Load
Line-to-Line
0.925 1.475 V
*Note: Voltage on RXDIN+ or RXDIN– should not exceed 1000 mV
PP
(single-ended)
All
Differential
IOs
t
F
t
R
80%
20%

SI5110-G-BC

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products OC-48, STM-16 SONET/SDH Transceiver 1:4 Deserializer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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