Operation modes M48T35, M48T35Y
8/28 Doc ID 2611 Rev 10
2 Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock
oscillator of the M48T35/Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible BYTEWIDE
clock information in the bytes with addresses 7FF8h-7FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 7FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T35/Y includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
The M48T35/Y also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
CC
is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
CC
. As V
CC
falls below the
battery backup switchover voltage (V
SO
), the control circuitry connects the battery which
maintains data and clock operation until valid power returns.
Table 2. Operating modes
2.1 READ mode
The M48T35/Y is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 15 address inputs defines which one of
the 32,768 bytes of data is to be accessed. Valid data will be available at the data I/O pins
within address access time (t
AVQV
) after the last address input signal is stable, providing that
the E
and G access times are also satisfied.
If the E
and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
ELQV
) or output enable access time (t
GLQV
).
The state of the eight three-state data I/O signals is controlled by E
and G. If the outputs are
activated before t
AVQV
, the data lines will be driven to an indeterminate state until t
AVQV
.
Mode V
CC
E G W DQ0-DQ7 Power
Deselect
4.75 to 5.5 V
or
4.5 to 5.5 V
V
IH
X X High Z Standby
WRITE V
IL
XV
IL
D
IN
Active
READ V
IL
V
IL
V
IH
D
OUT
Active
READ V
IL
V
IH
V
IH
High Z Active
Deselect V
SO
to V
PFD
(min)
(1)
1. See Table 11 on page 20 for details.
X = V
IH
or V
IL
;
V
SO
= battery backup switchover voltage.
X X X High Z CMOS standby
Deselect ≤ V
SO
(1)
X X X High Z Battery backup mode
