10
FN9181.3
October 31, 2008
The values of R and C should be selected to control the rate
of rise of VERR to the desired soft-start duration. The
soft-start duration may be calculated from Equation 6.
where V
SS
is the soft-start clamp voltage, V
be
is the base
emitter voltage drop of the transistor, and β is the DC gain of
the transistor. If β is sufficiently large, that term may be
ignored. The Schottky diode discharges the soft-start
capacitor so that the circuit may be reset quickly.
Gate Drive
The ISL6752 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical ON-resistance of the outputs
is 50Ω.
Overcurrent Operation
The cycle-by-cycle peak current control results in
pulse-by-pulse duty cycle reduction when the current
feedback signal exceeds 1.0V. When the peak current
exceeds the threshold, the active output pulse is
immediately terminated. This results in a well controlled
decrease in output voltage as the load current increases
beyond the current limit threshold. The ISL6752 will operate
continuously in an overcurrent condition.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased
by the leading edge blanking (LEB) interval. The effective
delay is the sum of the two delays and is nominally 105ns.
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be
accomplished by summing an external ramp with the current
feedback signal or by subtracting the external ramp from the
voltage feedback error signal. Adding the external ramp to
the current feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is expressed in Equation 7:
where S
n
is the slope of the sawtooth signal and t
SW
is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes Equation 8:
where S
e
is slope of the external ramp and:
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, and over-damped for
Q > 1, and under-damped for Q < 1. An under-damped
condition can result in current loop instability.
where D is the percent of on-time during a half cycle. Setting
Q = 1 and solving for S
e
yields Equation 11:
Since S
n
and S
e
are the on-time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by t
ON
to obtain the voltage change that occurs during t
ON
.
where V
n
is the change in the current feedback signal during
the on-time and V
e
is the voltage that must be added by the
external ramp.
V
n
can be solved for in terms of input voltage, current
transducer components, and output inductance yielding
Equation 13:
where R
CS
is the current sense burden resistor, N
CT
is the
current transformer turns ratio, L
O
is the output inductance,
V
O
is the output voltage, and N
S
and N
P
are the secondary
and primary turns, respectively.
The inductor current, when reflected through the isolation
transformer and the current sense transformer to obtain the
current feedback signal at the sense resistor yields
Equation 14:
where V
CS
is the voltage across the current sense resistor
and I
O
is the output current at current limit.
tRC 1
V
SS
V
be
VREF
0.001R
β
-------------------
+
-------------------------------------------
⎝⎠
⎜⎟
⎜⎟
⎛⎞
ln= S
(EQ. 6)
Fm
1
S
n
t
SW
------------------
=
(EQ. 7)
Fm
1
S
n
S
e
+()t
SW
------------------------------------
1
m
c
S
n
t
SW
--------------------------
==
(EQ. 8)
m
c
1
S
e
S
n
------ -
+=
(EQ. 9)
Q
1
π m
c
1D()0.5()
-------------------------------------------------
=
(EQ. 10)
S
e
S
n
1
π
---
0.5+
⎝⎠
⎛⎞
1
1D
-------------
1
⎝⎠
⎛⎞
=
(EQ. 11)
V
e
V
n
1
π
---
0.5+
⎝⎠
⎛⎞
1
1D
-------------
1
⎝⎠
⎛⎞
=
(EQ. 12)
V
e
t
SW
V
O
R
CS
N
CT
L
O
----------------------------------------
N
S
N
P
------- -
1
π
---
D0.5+
⎝⎠
⎛⎞
= V
(EQ. 13)
V
CS
N
S
R
CS
N
P
N
CT
------------------------
I
O
Dt
SW
2L
O
-------------------
V
IN
N
S
N
P
------- -
V
O
⎝⎠
⎜⎟
⎛⎞
+
⎝⎠
⎜⎟
⎛⎞
= V
(EQ. 14)
ISL6752
11
FN9181.3
October 31, 2008
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value.
Substituting Equations 13 and 14 into Equation 15 and
solving for R
CS
yields Equation 16:
For simplicity, idealized components have been used for this
discussion, but the effect of magnetizing inductance must be
considered when determining the amount of external ramp
to add. Magnetizing inductance provides a degree of slope
compensation to the current feedback signal and reduces
the amount of external ramp required. The magnetizing
inductance adds primary current in excess of what is
reflected from the inductor current in the secondary.
where V
IN
is the input voltage that corresponds to the duty
cycle D and L
m
is the primary magnetizing inductance. The
effect of the magnetizing current at the current sense
resistor, R
CS
, is expressed in Equation 18:
If ΔV
CS
is greater than or equal to V
e
, then no additional slope
compensation is needed and R
CS
becomes Equation 19:
If ΔV
CS
is less than V
e
, then Equation 16 is still valid for the
value of R
CS
, but the amount of slope compensation added
by the external ramp must be reduced by ΔV
CS
.
Adding slope compensation may be accomplished in the
ISL6752 using the CTBUF signal. CTBUF is an amplified
representation of the sawtooth signal that appears on the CT
pin. It is offset from ground by 0.4V and is 2x the peak-to-peak
amplitude of CT (0.4V to 4.4V). A typical application sums this
signal with the current sense feedback and applies the result
to the CS pin, as shown in Figure 6.
Assuming the designer has selected values for the RC filter
placed on the CS pin, the value of R9 required to add the
appropriate external ramp can be found by superposition.
Rearranging to solve for R9 yields Equation 21:
The value of R
CS
determined in Equation 16 must be
rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 14. The divider created
by R6 and R9 makes this necessary.
Example:
V
IN
= 280V
V
O
= 12V
L
O
= 2.0µH
Np/Ns = 20
Lm = 2mH
I
O
= 55A
Oscillator Frequency, F
SW
= 400kHz
Duty Cycle, D = 85.7%
N
CT
= 50
R6 = 499Ω
Solve for the current sense resistor, R
CS
, using Equation 16.
R
CS
= 15.1Ω.
V
e
V
CS
+ 1=
(EQ. 15)
R
CS
N
P
N
CT
N
S
------------------------
1
I
O
V
O
L
O
--------
t
SW
1
π
---
D
2
----
+
⎝⎠
⎛⎞
+
----------------------------------------------------
= Ω
(EQ. 16)
I
P
Δ
V
IN
Dt
SW
L
m
-----------------------------
= A
(EQ. 17)
ΔV
CS
ΔI
P
R
CS
N
CT
--------------------------
= V
(EQ. 18)
R
CS
N
CT
N
S
N
P
------- -
I
O
Dt
SW
2L
O
---------------
V
IN
N
S
N
P
------- -
V
O
⎝⎠
⎜⎟
⎛⎞
+
⎝⎠
⎜⎟
⎛⎞
V
IN
Dt
SW
L
m
-----------------------------
+
--------------------------------------------------------------------------------------------------------------------------------- -
=
(EQ. 19)
FIGURE 6. ADDING SLOPE COMPENSATION
R6
C4
R9
CTBUF
CS
1
2
4
3
5
6
7
89
10
11
12
13
14
15
16
R
CS
ISL6752
V
e
ΔV
CS
DV
CTBUF
0.4()0.4+()R6
R6 R9+
-------------------------------------------------------------------------------
= V
(EQ. 20)
R9
DV
CTBUF
0.4()V
e
ΔV
CS
0.4++()R6
V
e
ΔV
CS
-------------------------------------------------------------------------------------------------------------------
= Ω
(EQ. 21)
R
CS
R6 R9+
R9
----------------------
R
CS
=
(EQ. 22)
ISL6752
12
FN9181.3
October 31, 2008
Determine the amount of voltage, V
e
, that must be added to
the current feedback signal using Equation 13.
V
e
= 153mV
Next, determine the effect of the magnetizing current from
Equation 18.
ΔV
CS
= 91mV
Using Equation 21, solve for the summing resistor, R9, from
CTBUF to CS.
R9 = 30.1kΩ
Determine the new value of R
CS
, R’
CS
, using Equation 22.
R’
CS
= 15.4Ω
This discussion determines the minimum external ramp that
is required. Additional slope compensation may be
considered for design margin.
If the application requires deadtime of less than about
500ns, the CTBUF signal may not perform adequately for
slope compensation. CTBUF lags the CT sawtooth
waveform by 300ns to 400ns. This behavior results in a
non-zero value of CTBUF when the next half-cycle begins
when the deadtime is short.
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown in Figure 7.
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 20
and 21 require modification. Equation 20 becomes:
and Equation 21 becomes:
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain (>200) so as to
minimize the required base current. Whatever base current
is required reduces the charging current into CT and will
reduce the oscillator frequency.
ZVS Full-Bridge Operation
The ISL6752 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
To understand how the ZVS method operates, one must
include the parasitic elements of the circuit and examine a
full switching cycle.
In Figure 9, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
lumped together as switch capacitance, but represents all
parasitic capacitance in the circuit including winding
R6
C4
R9
R
CS
CT
CT
CS
1
2
4
3
5
6
7
8
ISL6752
VREF
FIGURE 7. ADDING SLOPE COMPENSATION USING CT
V
e
ΔV
CS
2D R6
R6 R9+
----------------------
= V
(EQ. 23)
R9
2D V
e
ΔV
CS
+()R6
V
e
ΔV
CS
-------------------------------------------------------------
= Ω
(EQ. 24)
FIGURE 8. BRIDGE DRIVE SIGNAL TIMING
CT
DEADTIME
OUTLL
OUTLR
OUTUR
OUTUL
RESDEL
WINDOW
RESONANT
DELAY
PWM
PWM
PWM
PWM
FIGURE 9. IDEALIZED FULL-BRIDGE
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
L
L
D2
D1
ISL6752

ISL6752AAZA-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers ZVS FL BRDG CNTRLR 16LD QSOP W/ANNEAL
Lifecycle:
New from this manufacturer.
Delivery:
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