9
FN9181.3
October 31, 2008
Voltages below 2.425V result in OUTLLN/OUTLRN being
advanced relative to OUTLL/OUTLR. Voltages above
2.575V result in OUTLLN/OUTLRN being delayed relative to
OUTLL/OUTLR. A voltage of 2.50V ±75mV results in zero
phase difference. A weak internal 50% divider from VREF
results in no phase delay if this input is left floating.
The range of phase delay/advance is either zero or 40ns to
300ns with the phase differential increasing as the voltage
deviation from 2.5V increases. The relationship between the
control voltage and phase differential is non-linear. The gain
(Δt/ΔV) is low for control voltages near 2.5V and rapidly
increases as the voltage approaches the extremes of the
control range. This behavior provides the user increased
accuracy when selecting a shorter delay/advance duration.
When the PWM outputs are delayed relative to the SR
outputs (VADJ < 2.425V), the delay time should not exceed
90% of the deadtime as determined by RTD and CT.
VERR - The control voltage input to the inverting input of the
PWM comparator. The output of an external error amplifier
(EA) is applied to this input, either directly or through an
opto-coupler, for closed loop regulation. VERR has a
nominal 1mA pull-up current source.
CTBUF - CTBUF is the buffered output of the sawtooth
oscillator waveform present on CT and is capable of
sourcing 2mA. It is offset from ground by 0.40V and has a
nominal valley-to-peak gain of 2. It may be used for slope
compensation.
Functional Description
Features
The ISL6752 PWM is an excellent choice for low cost ZVS
full-bridge applications requiring adjustable synchronous
rectifier drive. With its many protection and control features,
a highly flexible design with minimal external components is
possible. Among its many features are a very accurate
overcurrent limit threshold, thermal protection, a buffered
sawtooth oscillator output suitable for slope compensation,
synchronous rectifier outputs with variable delay/advance
timing, and adjustable frequency.
If synchronous rectification is not required, please consider
the ISL6753 controller.
Oscillator
The ISL6752 has an oscillator with a programmable
frequency range to 2MHz, which can be programmed with a
resistor and capacitor.
The switching period is the sum of the timing capacitor
charge and discharge durations. The charge duration is
determined by CT and a fixed 200µA internal current source.
The discharge duration is determined by RTD and CT.
where t
C
and t
D
are the charge and discharge times,
respectively, CT is the timing capacitor in Farads, RTD is the
discharge programming resistance in ohms, t
SW
is the
oscillator period, and F
SW
is the oscillator frequency. One
output switching cycle requires two oscillator cycles. The
actual times will be slightly longer than calculated due to
internal propagation delays of approximately 10ns/transition.
This delay adds directly to the switching duration, but also
causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very small
discharge currents are used, there will be increased error
due to the input impedance at the CT pin. The maximum
recommended current through RTD is 1mA, which produces
a CT discharge current of 20mA.
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from Equations 4 and 5:
Implementing Soft-Start
The ISL6752 does not have a soft-start feature. Soft-start
can be implemented externally using the components shown
in the following. The RC network governs the rate of rise of
the transistor’s base, which clamps the voltage at VERR.
t
C
11.5 10⋅
3
CT⋅≈ S
(EQ. 1)
t
D
0.06 RTD CT⋅⋅()50 10
9–
⋅+≈ S
(EQ. 2)
t
SW
t
C
t
D
+
1
F
SW
------------
== S
(EQ. 3)
D
t
C
t
SW
----------
=
(EQ. 4)
DT 1 D–=
(EQ. 5)
FIGURE 5. IMPLEMENTING SOFT-START
VREF
1
2
4
3
5
6
7
89
1
0
1
1
1
2
1
3
1
4
1
5
1
6
ISL6752
VERR
R
C
ISL6752
