Philips Semiconductors Product data
PCK2023
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
2003 Jul 31
15
POWER-UP SEQUENCE
Figure 6 shows the power-up sequence for the PCK2023. Once power is applied to the device, an internal sense circuit generates a signal
when the supply is above approximately 2 volts. This signal generates a series of timed signals that control the sequential event inside the
device. First, the multifunction pins are latched into the device. These latched signals are then used to define the mode of operation of the
device. A short time later, the PLL is enabled and begins running. After XX ms, the clock outputs are enabled and begin running
INTERNAL 3.3 V
SUPPLY
INTERNAL POWER
GOOD
SIGNAL LATCH
OPERATING MODE
SET/PLL START
OUTPUTS ENABLED
SW00854
Figure 6. Power-up sequence
DUT
C
L
V
DD
R
P
= 500 Ω
SW00855
R
S
R
S
R
S
= 33.2 Ω
R
P
= 50 Ω
HOST
HOST
CRYSTAL
14.318 MHz
Figure 7. Host clock measurements
