Philips Semiconductors Product data
PCK2023
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
2003 Jul 31
22
Component decoupling
Decoupling is another important consideration to ensure optimum
operation of the PCK2023. A first pass decoupling capacitor value
may be determined by applying the following equation:
C
bypass
+
1
2pF
psw
X
max
where
X
max
+
DV
DI
F
psw
+
X
max
2pL
psw
∆V is the maximum supply noise permitted (20 mV, for example)
∆I is the maximum current draw for the clock
L
psw
is the power supply lead inductance
F
psw
is the frequency below which the power supply wiring is
adequate
The maximum current may be determined by considering the
switching of the clock outputs and the capacitive load on these
outputs. The following equation may be used to determine the
current per output. Once the current for each clock output is
determined, they can be summed to determine the total switching
current.
i + C
load
dV
dt
Most of these values can be determined from the usage in the board
design. For example, the IOCLK has a specified edge rate of
1.25 ns typical when slewing between 0.7 and 2.4 volts and the
maximum C
load
is 30 pF. The HOST outputs are a special case
since, although the output either drives current or is off, only one
drives at a time, so the current is really steered rather than switched.
The act of steering the current reduces switching noise on these
supplies, therefore the HOST supplies require less decoupling. As a
starting point, assume the supply current for each HOST output is
equal to 1/2 the programmed output current.
Decoupling capacitors should be located as close to the power pins
on the IC as possible. The use of too much decoupling should be
avoided since it could cause oscillations on the part because of the
LC circuit (the IC leads act as inductors). Also, it is possible to cause
oscillations from resonance between the board inductance and
board capacitance. Two capacitors may be placed in parallel to
effectively extend the capacitance range of the decoupling since the
larger capacitor will have a self-resonance at a lower frequency than
the smaller capacitor. When using this method, the split between
values should be 100 (i.e., 0.1 µF and 0.001 µF).
Another consideration when selecting the decoupling capacitors is
the dielectric material of the capacitor. This will depend on the
frequency range of concern. For lower frequencies, Z5U material
may be used since this type of capacitor has a self-resonance in the
1 MHz to 20 MHz range. Capacitors of NPO have a self-resonance
much higher and are more for high frequency decoupling. Consult a
capacitor manufacture’s datasheet to determine the optimum
material type to use.
Additional filtering on the Analog supplies (AV
DD
) may be used to
reduce the noise coupled from the circuit board global V
DD
to the
internal V
DD
of the PCK2023. One way to do this is to use a PI filter.
The specific values should be selected to allow proper decoupling
on the pin side while rejecting the digital switching noise. A spectrum
analyzer can provide considerable insight to ensure optimum values
are selected. Measure the frequency content of the supply on either
side of the inductor to verify the values selected reduce the noise on
the component side of the filter. To provide the maximum isolation,
each AV
DD
line should have a separate filter since the internal
circuitry using these lines have very different switching
requirements. In general, pin 26 is strictly a static current draw and
should not have any switching noise. Great care has been taken to
reduce the sensitivity to supply noise, but there is a finite limit to the
capability to do this, therefore added filtering on the board should
enhance performance. Pin 46 is used as a supply to the internal
PLLs. This node will contain some high frequency switching noise
since the internal PLLs operate up to 200 MHz. Again, additional
filtering will improve the performance of the part. If a single filter is
used for both supplies, noise from the PLL supply (pin 46) can
couple int the I
ref
supply (pin 42) and increase the jitter of the HOST
outputs.
AV
DD
V
DD3.3
SW00858
Figure 12. PI filter for all analog V
DD
lines
I
ref
decoupling
Filtering on the I
ref
supply has already been discussed, but
additional filtering can be added on the I
ref
pin (pin 42) to perform
additional filtering of the reference current. This reference current is
critical to the performance of the HOST outputs since variation in
this current is directly proportional to jitter on the HOST outputs.
On-die decoupling has been included to reduce noise on this node,
but additional decoupling could also be used to further reduce any
noise. Care must be taken with this approach to ensure the
capacitor and reference resistor share the same ground. Placing
both components side by side is an optimum configuration. This
external capacitor should not exceed TBD pF to ensure the current
source inside the PCK2023 can supply enough charge for this node
to reach reference value (1.1 volt).
