7
INDUSTRIAL TEMPERATURE RANGE
IDT5T9821
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER
JTAG/ I
2
C SERIAL DESCRIPTION, CONT.
Bit Description
20 Divide selection for bank 2
19 Divide selection for bank 3
18 Divide selection for bank 3
17 Divide selection for bank 3
16 Divide selection for bank 3
15 Divide selection for bank 3
14 Divide selection for bank 4
13 Divide selection for bank 4
12 Divide selection for bank 4
11 Divide selection for bank 4
10 Divide selection for bank 4
9 Divide selection for bank 5
8 Divide selection for bank 5
7 Divide selection for bank 5
6 Divide selection for bank 5
5 Divide selection for bank 5
4 Divide selection for FB bank
3 Divide selection for FB bank
2 Divide selection for FB bank
1 Divide selection for FB bank
0 Divide selection for FB bank
JTAG/ I
2
C SERIAL CONFIGURATIONS:
OUTPUT ENABLE/DISABLE
Bit 59 (OMODE) Bit 56-52 (nsOE) Output
X (X) 0 and (L) Normal Operation
0 and (L) 1 or (H) Tri-Sate
1 or (H) 1 or (H) Gated
(1)
NOTE:
1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/
HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated. Bit 58 determines the level at which the outputs stop.
When Bit 58 is 0/ 1, the nQ and QFB are stopped in a HIGH/LOW state, while the
nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its
corresponding Bit 59 is 0, the outputs' disable state will be the tri-state.
JTAG/ I
2
C SERIAL CONFIGURATIONS:
POWERDOWN
PD Bit 59 (OMODE) Output
H X (X) Normal Operation
L 0 and (L) Tri-Sate
L 1 or (H) Gated
(1)
NOTE:
1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/
HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated. Bit 58 determines the level at which the outputs stop.
When Bit 58 is 0/ 1, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ
and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its
corresponding Bit 59 is 0, the outputs' disable state will be the tri-state.
JTAG/ I
2
C SERIAL CONFIGURATIONS:
CLOCK INPUT INTERFACE SELEC-
TION
(1)
Bit 31, 33, 35 Bit 30, 32, 34 Interface
0 0 Differential
(2)
0 1 2.5V LVTTL
1 1 1.8V LVTTL
NOTES:
1. All other states that are undefined in the table will be reserved.
2. Differential input interface for HSTL/eHSTL, LVEPECL (2.5V), and 2.5V/1.8V LVTTL.
JTAG/ I
2
C SERIAL CONFIGURATIONS:
OUTPUT DRIVE STRENGTH
SELECTION
(1)
Bit 37, 39, 41, Bit 36, 38, 40,
43, 45, 47 42, 44, 46 Interface
0 0 2.5V LVTTL
0 1 1.8V LVTTL
1 0 HSTL/eHSTL
NOTE:
1. All other states that are undefined in the table will be reserved.