A
A
T
T
P
P
A
A
4
4
B
B
1
1
6
6
Q
Q
F
F
4
4
B
B
N
N
R
R
C
C
S
S
W
W
Y
Y
o
o
u
u
r
r
U
U
l
l
t
t
i
i
m
m
a
a
t
t
e
e
M
M
e
e
m
m
o
o
r
r
y
y
S
S
o
o
l
l
u
u
t
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n
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!
!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 10 of 11
TIMING PARAMETER
Note:
1. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Parameter
Symbol
DDR4-2400
Units
Min Max
Clock cycle time at CL=17, CWL=12 tCK 0.833 <0.938
ns
Internal read command to first data tAA 14.16 18 ns
ACT to internal read or write delay time tRCD 14.16 ns
PRE command period tRP 14.16 ns
ACT to ACT or REF command period tRC 46.16 ns
ACTIVE to PRECHARGE command period tRAS 32 9*tREFI ns
Average clock high pulse width tCH(avg) 0.48 0.52 tCK
Average clock low pulse width tCL(avg) 0.48 0.52 tCK
DQS,
DQS
to DQ skew, per group, per access
tDQSQ - 0.16
ps
DQ output hold time from DQS,
DQS
tQH 0.76 -
tCK
DQ low-impedance time from CK,
CK
tLZ(DQ) -300 150
ps
DQ high-impedance time from CK,
CK
tHZ(DQ) - 150
ps
DQS,
DQS
READ Preamble
tRPRE 0.9 TBD
tCK
DQS,
DQS
differential READ Postamble
tRPST 0.33 TBD
tCK
DQS,
DQS
output high time
tQSH 0.4 -
tCK
DQS,
DQS
output low time
tQSL 0.4 -
tCK
DQS,
DQS
WRITE Preamble
tWPRE 0.9 -
tCK
DQS,
DQS
WRITE Postamble
tWPST 0.33 TBD
tCK
DQS,
DQS
low-impedance time (Referenced from RL-1)
tLZ(DQS) -300 150
ps
DQS,
DQS
high-impedance time (Referenced from RL+BL/2)
tHZ(DQS) - 150
ps
DQS,
DQS
differential input low pulse width
tDQSL 0.46 0.54
tCK
DQS,
DQS
differential input high pulse width
tDQSH 0.46 0.54
tCK
DQS,
DQS
rising edge to CK,
CK
rising edge
tDQSS -0.27 0.27
tCK
DQS,
DQS
falling edge setup time to CK,
CK
rising edge
tDSS 0.18 -
tCK
DQS,
DQS
falling edge hold time to CK,
CK
rising edge
tDSH 0.18 -
tCK
DLL locking time tDLLK
768 -
nCK
Internal READ Command to PRECHARGE Command delay tRTP max(4nCK,7.5ns) -
Delay from start of internal write trans-action to internal read command for different bank group tWTR_S max(2nCK,2.5ns) -
Delay from start of internal write trans-action to internal read command for same bank group tWTR_L max(4nCK,7.5ns) -
WRITE recovery time tWR 15 - ns
Mode Register Set command cycle time tMRD 8 - nCK
Mode Register Set command update delay tMOD max(24nCK,15ns) -
CAS
to
CAS
command delay for same bank group
tCCD 6 -
nCK
Auto precharge write recovery + precharge time tDAL tWR + roundup (tRP / tCK) nCK
Multi-Purpose Register Recovery Time tMPRR 1 - nCK
ACTIVE to ACTIVE command delay to same bank group for 1KB page size tRRD max(4nCK,5.3ns) -
Four activate window for 1KB page size tFAW max(20nCK,21ns) -
Command and Address setup time to CK,
CK
referenced to Vih(ac) / Vil(ac) levels
tIS(base) 62 -
ps
Command and Address hold time from CK,
CK
referenced to Vih(ac) / Vil(ac) levels
tIH(base) 87 -
ps
Power-up and RESET calibration time tZQinit 1024 - nCK
Normal operation Full calibration time tZQoper 512 - nCK
Normal operation short calibration time tZQCS 128 - nCK
Exit Reset from CKE HIGH to a valid command
tXPR
max (5nCK,tRFC( min)+
10ns)
-
Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
tXP max(4nCK,6ns) -
Asynchronous RTT turn-on delay (Power-Down with DLL frozen) tAONAS 1 9 ns
Asynchronous RTT turn-off delay (Power-Down with DLL frozen) tAOFAS 1 9 ns
RTT dynamic change skew tADC 0.3 0.7 tCK
8Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval tRFC 350 - ns
Average periodic refresh interval (0°C ≤ TCASE ≤ 85 °C) tREFI 7.8 7.8 us
Average periodic refresh interval (85°C ≤ TCASE ≤ 95 °C) tREFI 3.9 3.9 us
Exit Self Refresh to commands not requiring a locked DLL tXS tRFC(min)+10ns -
Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - nCK
Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCK
Write leveling output delay tWLO 0 9.5 ns
Write leveling output error tWLOE TBD TBD ns
