A
A
T
T
P
P
A
A
4
4
B
B
1
1
6
6
Q
Q
F
F
4
4
B
B
N
N
R
R
C
C
S
S
W
W
Y
Y
o
o
u
u
r
r
U
U
l
l
t
t
i
i
m
m
a
a
t
t
e
e
M
M
e
e
m
m
o
o
r
r
y
y
S
S
o
o
l
l
u
u
t
t
i
i
o
o
n
n
!
!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 5 of 11
CS0A_n -> CS0_n: SDRAMs U[0:4], U[13:17]
CS0B_n -> CS0_n: SDRAMs U[5:8], U[9:12]
ODT0B -> ODT: SDRAMs U[5:8], U[9:12]
ODT0A -> ODT: SDRAMs U[0:4], U[13:17]
CKE0A -> CKE: SDRAMs U[0:4], U[13:17]
CKE0B -> CKE: SDRAMs U[5:8], U[9:12]
C0, C1, C2
C0B, C1B, C2B -> C1, C1, C2: SDRAMs U[5:8], U[9:12]
C0A, C1A, C2A -> C0, C1, C2: SDRAMs U[0:4], U[13:17]
Y1(_t, _c) -> CK1A(_t, _c): SDRAMs U[13:17]
Y3(_t, _c) -> CK3A(_t, _c): SDRAMs U[0:4]
ERROR_IN_n <- ALERT_n: ALL SDRAMs
QRST_n -> RESET_n:ALL SDRAMs
ALERT_n
PARA -> PAR, ACT_n: SDRAMs U[0:4], U[13:17]
PARB -> PAR, ACT_n: SDRAMs U[5:8], U[9:12]
A[0:17]B->A[0:17]:DDR4 SDRAMs: U[5:8], U[9:12]
A[0:17]A->A[0:17]:DDR4 SDRAMs: U[0:4], U[13:17]
BA[0:1]A->BA[0:1]:DDR4 SDRAMs: U[0:4], U[13:17]
BA[0:1]B->BA[0:1]:DDR4 SDRAMs: U[5:8], U[9:12]
BG[0:1]B->BG[0:1]:DDR4 SDRAMs: U[5:8], U[9:12]
BA[0:1]
Y2(_t, _c) -> CK2A(_t, _c): SDRAMs U[5:8]
Y0(_t, _c) -> CK0A(_t, _c): SDRAMs U[9:12]
CK1_n
CK1_t
CK0_n
CK0_t
R
E
G
I
S
T
E
R
RESET_n
A0-A17
PARITY,ACT_n
CS0_n
CKE0
BG[0:1]
ODT0
BG[0:1]A->BG[0:1]:DDR4 SDRAMs: U[0:4], U[13:17]
