BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
10/24
www.rohm.com
2009.06 - Rev.A
© 2009 ROHM Co., Ltd. All rights reserved.
Switching characteristics (Unless otherwise specified, VDD=5V, VSS=0V, Ta=25)
Parameter
Symbol
Limit
Unit
Condition
Min. Typ. Max. VDD(V)
Minimum Clock Pulse Width
t
w
1000 - - ns 3
-
500 - - ns 5
Minimum Latch Pulse Width
(LCK)
tw
(LCK)
1000 - - ns 3
-
500 - - ns 5
Setup Time
(LCKCLOCK)
t
s
400 - - ns 3
-
200 - - ns 5
Setup Time
(DATACLOCK)
t
su
400 - - ns 3
-
200 - - ns 5
Hold Time
(CLOCKDATA)
t
H
400 - - ns 3
-
200 - - ns 5
Propagation
(LCKOUTPUT QX)
t
PLZ
(LCK)
- 90 - ns 3
RL=5k
CL=10pF
- 55 - ns 5
tPZL
(LCK)
- 115 - ns 3 R
L=5k
CL=10pF
- 50 - ns 5
Propagation
( OE OUTPUT QX)
t
PLZ
- 70 - ns 3 R
L=5k
C
L=10pF
- 45 - ns 5
tPZL
- 80 - ns 3 R
L=5k
C
L=10pF
- 35 - ns 5
Switching Time Test Circuit
Fig. 5
CLOCK
Pulse
Gen.
DATA
Pulse
Gen.
Q11
RL
±25V
Q0
RL
±25V
VDD
GND (Vss)
Pulse
Gen.
Pulse
Gen.
LCK
OE
GND (Vss)
GND (Vss)
CL
CL
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
11/24
www.rohm.com
2009.06 - Rev.A
© 2009 ROHM Co., Ltd. All rights reserved.
BU2092F/BU2092FV
Switching Time Test Waveforms
Fig. 6
CLOCK
DATA
t
SU
90%
10%
90% 90%
t
H
90% 90%
10%
90%
10%
t
W
t
W
50%
LCK
50%
90%
10%
t
S
90%
t
W
(CLK)
50%
50%
OE
Qx
t
PLZ
(LCK) t
PZL
(LCK)
10%
50%
10%
t
PLZ
50%
t
PZL
VDD
GND
(
VSS
)
VDD
GND
(
VSS
)
VDD
GND
(
VSS
)
VDD
GND
(
VSS
)
VDD
GND
(
VSS
)
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
12/24
www.rohm.com
2009.06 - Rev.A
© 2009 ROHM Co., Ltd. All rights reserved.
BU2099FV
Pin descriptions
Pin No. Pin Name I/O Function
1 V
SS
- GND
2 N.C. - Non connected
3 DATA I Serial Data Input
4 CLOCK I Shift clock of Shift register (Rising Edge Trigger)
5 LCK I Latch clock of Storage register (Rising Edge Trigger)
617
Q0
Q11
(Qx)
O
Parallel Data Output (Nch Open Drain FET)
Latch Data L H
Output FET ON OFF
18 SO O Serial Data Output
19 OE I Output Enable Control Input OE pin is pulled down to Vss.
20 V
DD
- Power Supply
Timing chart
Fig. 7
1. After the power is turned on and the voltage is stabilized, LCK should be activates, after clocking 12 data bits into
the DATA terminal.
2. Qx parallel output data of the shift register is set after the 12
th
clock by the LCK.
3. Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.
4. Data retained in the internal latch circuit is output when the OE is in the “L” section.
5. The final stage data of the shift register is output to the SO by synchronizing with the rise time of the CLOCK.
Truth Table
Input
Function
CLOCK DATA LCK
OE
× × × H All the output data output “H” with pull-up.
× × × L The Q0Q11 output can be enable and output the data of storage register.
L × ×
Store “L” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
H × ×
Store “H” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
× × ×
The data of shift register has no change.
SO outputs the final stage data of shift register with synchronized falling
edge of CLOCK, not controlled by OE.
× ×
× The data of shift register is transferred to the storage register.
× ×
× The data of storage register has no change.
The Q0Q11 output have a Nch open drain Tr. The Tr is ON when data from shift register is “L”, and Tr is OFF when data is “H”.
CLOCK
LCK
DATA
DATA12 DATA11 DATA10 DATA2 DATA1
OE
Qx
Previous DATA DATA
SO
Previous
DATA 11
Previous
DATA 11
DATA12
DATA11
“H”

BU2152FS-E2

Mfr. #:
Manufacturer:
Description:
Gate Drivers DRVR SER/PAR 24B
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New from this manufacturer.
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