BU2152FS-E2 Datasheet BU2152FS-E2, BU2092FV-E2, BU2099FV-E2 | P7-P9

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

Technical Note

7/24

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2009.06 - Rev.A

【BU2050F】

●Pin descriptions

Pin No. Pin Name Function

1 P3

Parallel Data Output

2 P4

3 P5

4 VSS GND

5 P6

Parallel Data Output

6 P7

7 P8

8 DATA Serial Data Input

9 CLK Clock Signal Input

10 STB

Strobe Signal Input

In case of “L”, the data of shift register outputs.

In case of “H”, all parallel outputs and data of latch circuit do not change.

11 CLR

Reset Signal Input

In case of “L”, the data of latch circuit reset, and all parallel output (P1～P8) can be L.

Normally CLR=H

12 P1

Parallel Data output

13 P2

14 VDD Power Supply

●Timing chart

Fig. 2

1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into the

DATA pin.

2. Pn parallel output data of the shift register is set after the 8

clock by the STB.

3. Since the STB is level latch, data is retained in the “L” section and renewed in the “H” section of the STB.

［Function explanation］

・ A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is “L”, the latch

circuit is reset non-synchronously without the other input condition, and all parallel output can be “L”.

・ A serial data inputted from DATA terminal is read in shift register with synchronized rising of clock.

In case of STB is “L” (CLR is ”H”), transmit the data which read in the shift register to latch circuit, and

outputs from the parallel data output terminal (P1～P8).

In case of STB is “H”, all parallel outputs and the data of latch do not change.

CLK

STB

DATA

DATA8 DATA7 DATA6 DATA2 DATA1

Previous DATA DATA

CLR

“L”

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

Technical Note

8/24

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2009.06 - Rev.A

●Switching characteristics (Unless otherwise specified, VDD=4.5 to 5.5V, Ta=25℃)

Parameter Symbol

Limit

Unit Condition

Min. Typ. Max.

Set up time (DATA-CLK) t

20 - - ns -

Hold time (DATA-CLK) t

20 - - ns -

Set up time CLK)STB( 

SSTB

30 - - ns -

Hold time CLK)STB( 

HSTB

30 - - ns -

Propagation P8)P1CLR( ～

PDPCK

- - 100 ns P1～P8 terminal load 20pF or less

Propagation P8)P1STB( ～

PDPSTB

- - 80 ns P1～P8 terminal load 20pF or less

Propagation

P8)P1CLR( ～

PDPCLR

- - 80 ns P1～P8 terminal load 20pF or less

Maximum clock frequency f

MAX

5 - - MHz -

●Switching Time Test Waveform

Fig. 3

CLK

DATA

STB

CLR

1 2 8 9 10 11 12

MAX

HSTB

SSTB

PDPSTB

PDPCL

PDPCK

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

Technical Note

9/24

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2009.06 - Rev.A

【BU2092F/BU2092FV】

●Pin descriptions

●Timing chart

Fig. 4

1. After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits into

the DATA terminal.

2. Qx parallel output data of the shift register is set after the 12

clock by the LCK.

3. Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.

4. Data retained in the internal latch circuit is output when the OE is in the “L” section.

［Truth Table］

Input

Function

CLOCK DATA LCK OE

× × × H Output (Q0～Q11) Disable

× × × L Output (Q0～Q11) Enable

L × ×

Store “L” in the first stage data of shift register, the previous stage data in the

others. (The conditions of storage register and output have no change.)

H × ×

Store “H” in the first stage data of shift register, the previous stage data in the

others. (The conditions of storage register and output have no change.)

× × × The data of shift register has no change.

× × × The data of shift register is transferred to the storage register.

× × × The data of storage register has no change.

Pin No. Pin Name I/O Function

1 V

- GND

2 DATA I Serial Data Input

3 CLOCK I Shift clock of DATA (Rising Edge Trigger)

4 LCK I Latch clock of DATA (Rising Edge Trigger)

5～11,

14～18

Q0～Q11 O

Parallel Data Output (Nch Open Drain FET)

Latch Data L H

Output FET ON OFF

12, 13 N.C. - Non connected

17 OE I Output Enable (“H” level : output FET is OFF)

18 V

- Power Supply

CLOCK

LCK

DATA

DATA11 DATA10 DATA9 DATA1 DATA0

Previous DAT

DATA11～0

“H”

Note) Diagram shows a status where a pull-up resistor is connected to output.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

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BU2152FS-E2

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