DS1085L
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A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
Figure 2. DATA TRANSFER ON 2-WIRE SERIAL BUS
Figures 2, 3, and 4 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state
of the R/W bit, two types of data transfer are possible:
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus is not released.
The DS1085L can operate in the following two modes:
1) Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception
of the slave address and direction bit.
2) Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS1085L while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
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SLAVE ADDRESS
A control byte is the first byte received following the START condition from the master device. The
control byte consists of a 4-bit control code; for the DS1085L, this is set as 1011 binary for read and write
operations. The next three bits of the control byte are the device select bits (A2, A1, A0). The address bits
to which the DS1085L responds are factory set to 000, but can be altered by writing new values to the
ADDR register. After the new address is written, the DS1085L responds only to the new address bit
values. The master uses this to select which of eight devices are to be accessed. The set bits are in effect
the three least significant bits of the slave address. The last bit of the control byte (R/W) defines the
operation to be performed. When set to a 1, a read operation is selected; when set to a 0, a write operation
is selected. Following the START condition, the DS1085L monitors the SDA bus checking the device
type identifier being transmitted. Upon receiving the 1011 code and appropriate device select bits, the
slave device outputs an acknowledge signal on the SDA line.
Figure 3. TIMING DIAGRAM
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Figure 4. 2-WIRE SERIAL COMMUNICATION WITH DS1085L

DS1085LZ-25B2+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Programmable Oscillators 3.3V EconOscillator f Synthesizer
Lifecycle:
New from this manufacturer.
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