DS1085LZ-5+W Datasheet DS1085LZ-25B2+, DS1085LZ-5+T, DS1085LZ-5+W | P10-P12

DS1085L

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COMMAND SET

Data and control information is read from and written to the DS1085L in the format shown in Figure 3.

To write to the DS1085L, the master issues the slave address of the DS1085L and the R/ W bit is set to 0.

After receiving an acknowledge, the bus master provides a command protocol. After receiving this

protocol, the DS1085L issues an acknowledge, and then the master can send data to the DS1085L. If the

DS1085L is to be read, the master must send the command protocol as before, and then issue a repeat

START condition and then the control byte again, this time with the R/ W bit set to 1 to allow reading of

the data from the DS1085L. The command set for the DS1085L is listed as follows:

Access DAC [08h]

If R/ W is 0, this command writes to the DAC register. After issuing this command, the next data byte

values are written into the DAC register. If R/ W is 1, the next data bytes read are the values stored in the

DAC register. This is a 2-byte transfer, the first byte contains the eight MSBs, and the second byte

contains the two LSBs in the most significant positions of the data byte. The remaining six bits are

ignored and can be written with any value (if read, these bits are 0).

Access OFFSET [0Eh]

If R/ W is 0, this command writes to the OFFSET register. After issuing this command, the next data byte

value is written into the OFFSET register. If R/ W is 1, the next data byte read is the value stored in the

OFFSET register. This is a single-byte transfer of which only the five LSBs (last five bits) are used. The

remaining three bits can be written with any value to complete the data byte (if read, these bits are 1).

Access DIV [01h]

If R/ W is 0, this command writes to the DIV register. After issuing this command, the next data byte

values are written into the DIV register. If R/ W is 1, the next data bytes read are the values stored in the

DIV register. This register has a 10-bit value. The upper eight bits are sent first, followed by a second

byte that contains the two LSBs of the register value in the most significant positions of the data byte.

The remaining six bits are ignored and can be set to any value (if read, these bits are 0).

Access MUX [02h]

If R/ W is 0, this command writes to the MUX register. After issuing this command, the next data byte

values are written into the MUX register. If R/

W is 1, the next data bytes read are the values stored in the

MUX register. This register has a 10-bit value. The upper eight bits are sent first, followed by a second

byte that contains the two LSBs of the register value in the most significant positions of the data byte.

The remaining six bits are ignored and can be set to any value (if read, these bits are 0).

Access ADDR [0Dh]

If R/ W is 0, this command writes to the ADDR register. After issuing this command, the next data byte

value is written into the ADDR register. If R/ W is 1, the next data byte read is the value stored in the

ADDR register. This is a single-byte transfer. This register has a 5-bit value, the first three bits of a write

can be any value followed by the five active bits (if read, the first three bits are 0).

DS1085L

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Access RANGE [37h]

If R/ W is 1, the next data bytes read are the values stored in the RANGE register. This register has a 14-

bit value. The upper eight bits are sent first, followed by a second byte that contains the five LSBs of the

contain the OS value for the frequency adjust Table 6. The register is read-only.

Write E2 [3Fh]

If WC = 0, the EEPROM is automatically written to at the end of each write command. This is a

DEFAULT condition. In this case the command “WRITE E2” is not needed. If WC = 1, the EEPROM is

written when the “WRITE E2” command is issued. On receipt of the “WRITE E2” command, the

contents of the DAC, OFFSET, ADDR, DIV and MUX registers are written into the EEPROM, thus

locking in the register settings.

EXCEPTION: The DAC, OFFSET, ADDR, DIV, and MUX registers are always automatically written to

EEPROM after a write to the ADDR register regardless of the value of the WC bit.

DS1085L

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2-WIRE SERIAL DATA BUS

The DS1085L communicates through a 2-wire serial interface. A device that sends data onto the bus is

defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is

called a “master.” The devices that are controlled by the master are “slaves.” A master device that

generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions

must control the bus. The DS1085L operates as a slave on the 2–wire bus. Connections to the bus are

made through the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (see Figure 2):

§ Data transfer can be initiated only when the bus is not busy.

§ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is high are interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is

HIGH, defines a START condition.

Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is

HIGH, defines the STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the data line

is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed

during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited, and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a

ninth bit.

Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are

defined. The DS1085L works in both modes.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the

byte has been received. The master device must generate an extra clock pulse that is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of

course, setup and hold times must be taken into account. When the DS1085L EEPROM is being written

to, it is not able to perform additional responses. In this case, the slave DS1085L sends a not acknowledge

to any data transfer request made by the master. It resumes normal operation when the EEPROM

operation is complete.

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DS1085LZ-5+W

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DS1085LZ-5+W

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