DS1085LZ-5+W Datasheet DS1085LZ-25B2+, DS1085LZ-5+T, DS1085LZ-5+W | P7-P9

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The functions of the individual bits are described in the following paragraphs.

DIV1 (Default Setting = 0)

This bit allows the output of the prescaler P1 to be routed directly to the

OUT1 pin (DIV1 = 1). In this condition, the N divider is bypassed so the

programmed value of N is ignored. If DIV1 = 0, the N divider functions

normally.

EN0 (Default Setting = 1)

If EN0 = 1 and PDN0 = 0, the CTRL0 functions as an output enable for OUT0, the frequency of the

output being determined by the SEL0 bit.

If PDN0 = 1, the EN0 bit is ignored, CTRL0 functions as a power-down, and OUT0 is always enabled on

power-up, its frequency determined by the SEL0 bit.

If EN0 = 0, the function of CTRL0 is determined by the SEL0 and PDN0 bits (see Table 2).

SEL0 (Default Setting = 1)

If SEL0 = 1 and EN0 = PDN0 = 0, the CTRL0 pin determines whether the prescaler is bypassed,

controlling the output frequency.

If CTRL0 = 0, the output frequency equals MCLK.

If CTRL0 = 1, the output frequency equals MCLK/M.

If either EN0 or PDN0 = 1, the CTRL0 pin functions as an output enable or power-down and the SEL0

bit determines whether the prescaler is bypassed, thus controlling the output frequency.

If SEL0 = 0, the output is MCLK, the master clock frequency.

If SEL0 = 1, the output is the output frequency of the M prescaler (see Table 2).

PDN0 (Default Setting = 0)

If PDN0 = 1, the CTRL0 performs a power-down function, regardless of the setting of the other bits.

If PDN0 = 0, the function of CTRL0 is determined by the values of EN0 and SEL0 (see Table 2).

0M0, 0M1, 1M0, 1M1 (Default Setting = 0)

These bits set the prescaler’s (P0 and P1) divisor (M) to 1, 2, 4, or 8 (see Table 7a and 7b).

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Table 7a. PRESCALER P0 DIVISOR M SETTINGS

0M1 0M0 PRESCALER P0

DIVISOR “M”

0 0 1*

0 1 2

1 0 4

1 1 8

*Factory Default Setting

Table 7b. PRESCALER P1 DIVISOR M SETTINGS

1M1 1M0 PRESCALER P1

DIVISOR “M”

0 0 1*

0 1 2

1 0 4

1 1 8

*Factory Default Setting

NOTE:

When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case for

situations when OUT0 is not used. Under these conditions all the circuitry associated with OUT0 is

powered down. OUT0 is powered down (see Table 2).

PDN1 (Default Setting = 0)

If PDN1 = 1, CTRL1 functions as a power-down (see Table 3).

· If PDN1 = 0, CTRL1 functions as an output enable for OUT1 (see Table 3).

NOTES FOR OUTPUT ENABLE AND POWER-DOWN:

1) Both enables are “smart” and wait for the output to be low before going High-Z.

2) A power-down sequence first disables both outputs before powering down the device.

3) On power-up, the outputs are disabled until the clock has stabilized (~8000 cycles).

4) In power-down mode the device cannot be programmed.

5) A power-down command must persist for at least two cycles of the lowest output frequency plus

10µs.

DIV WORD (N) (Address 01h)

MSB LSB MSB LSB

N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 X X X X X X

First Data Byte Second Data Byte

X = Don’t care.

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The DIV word sets the programmable divider. These 10 bits (N0–N9) determine the value of the

programmable divider (N). The range of divisor values is from two to 1025, and is equal to the

programmed value of N plus 2 (see Table 8).

Table 8. PROGRAMMABLE DIVISOR N VALUES

BIT VALUE DIVISOR (N)

00000000 00XXXXXX 2*

00000000 01XXXXXX 3

— —

11111111 11XXXXXX 1025

* Factory Default Setting

ADDR BYTE (Address 0Dh)

MSB LSB

NAME — — — — WC A2 A1 A0

Factory

Default

X X X X

0 0 0 0

X = Don’t care.

A0, A1, A2 (Default Setting = 000)

These device select bits determine the 2-wire address of the device.

WC (Default Setting = 0)

This bit determines when/if the EEPROM is written to after register contents have been changed. If

WC = 0, EEPROM is written automatically after a write register command. If WC = 1, EEPROM is only

written when the “WRITE” command is issued. In applications where the register contents are frequently

rewritten, WC should be set to 1; otherwise, it is necessary to wait for an EEPROM write cycle to

complete (up to 10ms) between writing to the registers. Regardless of the value of the WC bit, when the

ADDR register (A0, A1, A2) is written, the current value in all registers (DAC, OFFSET, DIV, MUX,

and ADDR) are immediately to the EEPROM.

RANGE REGISTER (Address 37h)

MSB LSB

OS5 OS4 OS3 OS2 OS1 X X X X X X X X X X X

The first five bits of the RANGE register contain the default OFFSET value. The decimal value of the

RANGE register is the value OS that is referred to in Table 6. The RANGE register is read-only.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

DS1085LZ-5+W

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