LTC3857
22
3857fd
APPLICATIONS INFORMATION
4. EXTV
CC
Connected to an Output-Derived Boost Network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTV
CC
to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with the capacitive charge
pump shown in Figure 9. Ensure that EXTV
CC
< V
IN
.
Topside MOSFET Driver Supply (C
B
, D
B
)
External bootstrap capacitors, C
B
, connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor C
B
in the Functional Diagram is charged though
external diode D
B
from INTV
CC
when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the C
B
voltage across the gate-source of the
desired MOSFET. This enhances the top MOSFET switch
and turns it on. The switch node voltage, SW, rises to V
IN
and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: V
BOOST
=
V
IN
+ V
INTVCC
. The value of the boost capacitor, C
B
, needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the external
Schottky diode must be greater than V
IN(MAX)
.
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then there
is no change in efficiency.
Fault Conditions: Current Limit and Current Foldback
The LTC3857 includes current foldback to help limit
load current when the output is shorted to ground. If
the output voltage falls below 70% of its nominal output
level, then the maximum sense voltage is progressively
lowered to about half of its maximum selected value.
Under short-circuit conditions with very low duty cycles,
the LTC3857 will begin cycle skipping in order to limit
the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
is determined by the minimum on-time, t
ON(MIN)
, of the
LTC3857 (≈90ns), the input voltage and inductor value:
ΔI
L(SC)
=t
ON(MIN)
V
IN
L
The resulting average short-circuit current is:
I
SC
≈50%•I
LIM(MAX)
1
2
ΔI
L(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the control-
ler is operating.
A comparator monitors the output for overvoltage condi-
tions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously for
as long as the overvoltage condition persists; if V
OUT
returns
to a safe level, normal operation automatically resumes.
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
EXTV
CC
V
IN
TG1
SW
BG1
PGND
1/2 LTC3857
R
SENSE
V
OUT
VN2222LL
C
OUT
3857 F09
MBOT
MTOP
C
IN
L
BAT85 BAT85
BAT85
Figure 9. Capacitive Charge Pump for EXTV
CC
LTC3857
23
3857fd
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3857 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked to
the rising edge of an external clock signal applied to the
PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET
is thus 180 degrees out of phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the inter-
nal oscillators frequency, f
OSC
, then current is sourced
continuously from the phase detector output, pulling
up the VCO input. When the external clock frequency
is less than f
OSC
, current is sunk continuously, pulling
down the VCO input. If the external and internal fre-
quencies are the same but exhibit a phase difference,
the current sources turn on for an amount of time
corresponding to the phase difference. The voltage at the
VCO input is adjusted until the phase and frequency of
the internal and external oscillators are identical. At the
stable operating point, the phase detector output is high
impedance and the internal filter capacitor, C
LP
, holds the
voltage at the VCO input.
Note that the LTC3857 can only be synchronized to an
external clock whose frequency is within range of the
LTC3857’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Typically, the external clock (on the PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.1V.
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock
and synchronization. Although it is not required that the
free-running frequency be near external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTV
CC
DC Voltage 535kHz
Resistor DC Voltage 50kHz-900kHz
Any of the Above External Clock Phase–Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time duration
that the LTC3857 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
t
ON(MIN)
<
V
OUT
V
IN
f
()
Figure 10. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
FREQ PIN RESISTOR (k)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
3857 F10
400
200
500
700
900
300
100
0
65 75 85 95 105 115
125
LTC3857
24
3857fd
APPLICATIONS INFORMATION
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3857 is approximately
95ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3857 circuits: 1) IC V
IN
current, 2) IN-
TV
CC
regulator current, 3) I
2
R losses, 4) topside MOSFET
transition losses.
1. The V
IN
current is the DC input supply current given
in the Electrical Characteristics table, which excludes
MOSFET driver and control currents. V
IN
current typi-
cally results in a small (<0.1%) loss.
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTV
CC
to ground. The resulting dQ/dt is a current
out of INTV
CC
that is typically much larger than the
control circuit current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of
the topside and bottom side MOSFETs.
Supplying INTV
CC
from an output-derived power source
through EXTV
CC
will scale the V
IN
current required for
the driver and control circuits by a factor of (Duty Cycle)/
(Efficiency). For example, in a 20V to 5V application,
10mA of INTV
CC
current results in approximately 2.5mA
of V
IN
current. This reduces the midcurrent loss from
10% or more (if the driver was powered directly from
V
IN
) to only a few percent.
3. I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor and input and output capacitor ESR. In continuous
mode the average output current flows through L and
R
SENSE
, but is chopped between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs have
approximately the same R
DS(ON)
, then the resistance
of one MOSFET can simply be summed with the resis-
tances of L, R
SENSE
and ESR to obtain I
2
R losses. For
example, if each R
DS(ON)
= 30m, R
L
= 50m, R
SENSE
= 10m and R
ESR
= 40m (sum of both input and
output capacitance losses), then the total resistance
is 130m. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of V
OUT
for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (t
y
pically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) • V
IN
• 2 • I
O(MAX)
• C
RSS
• f

LTC3857IUH#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Low IQ, Dual, 2-Phase Synchronous Step Down Controller
Lifecycle:
New from this manufacturer.
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