10
Package Characteristics
All Typicals at T
A
= 25°C
Parameter Sym. Package* Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output V
ISO
3750 V rms RH ≤ 50%, 5, 6
Momentary With- t = 1 min.,
stand Voltage** T
A
= 25°C
Input-Output R
I-O
10
12
Ω V
I-O
= 500 Vdc 4, 8
Resistance
Input-Output C
I-O
0.6 pF f = 1 MHz, 4, 8
Capacitance T
A
= 25°C
Input-Input I
I-I
Dual Channel 0.005 µA RH ≤ 45%, 19
Insulation t = 5 s,
Leakage Current V
I-I
= 500 V
Resistance R
I-I
Dual Channel 10
11
Ω 19
(Input-Input)
Capacitance C
I-I
Dual 8-pin DIP 0.03 pF f = 1 MHz 19
Dual SO-8 0.25
*Ratings apply to all devices except otherwise noted in the Package column.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), your equip-
ment level safety specication or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
†For 8-pin DIP package devices (HCPL-261A/261N/263A/263N) only.
(Input-Input)
OPT 020† 5000
5, 7
Notes:
1. Peaking circuits may be used which produce transient input currents up to 30 mA, 50 ns maximum pulse width, provided the average cur-
rent does not exceed 10 mA.
2. 1 minute maximum.
3. Derate linearly above 80 °C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
4. Each channel.
5. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
6. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
RMS
for 1 second (leakage detec-
tion current limit, I
I-O
≤ 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in the IEC/EN/
DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.
7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V
RMS
for 1 second (leakage detec-
tion current limit, I
I-O
≤ 5 µA).
8. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together.
9. The t
PLH
propagation delay is measured from the 1.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of
the output pulse.
10. The t
PHL
propagation delay is measured from the 1.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of
the output pulse.
11. Propagation delay skew (t
PSK
) is equal to the worst case dierence in t
PLH
and/or t
PHL
that will be seen between any two units under the same
test conditions and operating temperature.
12. Single channel products only (HCPL-261A/261N/061A/061N).
13. Common mode transient immunity in a Logic High level is the maximum tolerable |dV
CM
/dt| of the common mode pulse, V
CM
, to assure that
the output will remain in a Logic High state (i.e., V
o
> 2.0 V).
14. Common mode transient immunity in a Logic Low level is the maximum tolerable |dV
CM
/dt| of the common mode pulse, V
CM
, to assure that
the output will remain in a Logic Low state (i.e., V
O
< 0.8 V).
15. For sinusoidal voltages
(|dV
CM
/dt|)max = πf
CM
V
CM(P-P)
.
16. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoup ler as shown in Figure 19. Total
lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
17. Pulse Width Distortion (PWD) is dened as the dierence between t
PLH
and t
PHL
for any given device.
18. No external pull up is required for a high logic state on the enable input of a single channel product. If the V
E
pin is not used, tying V
E
to V
CC
will result in improved CMR performance.
19. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel parts only.
