HCPL-063A Datasheet HCPL-263N-000E, HCPL-061A-500E, HCPL-261A-000E | P16-P17

Figure 24. CMOS gate drive circuit for HCPL-261A/-261N families.

Figure 23. TTL open-collector/open drain gate drive circuit for

HCPL-261A/-261N families.

coup lers, dierences in propaga tion delays will cause

the data to arrive at the outputs of the opto couplers at

dierent times. If this dierence in propagation delay

is large enough it will determine the maximum rate at

which parallel data can be sent through the optocou-

plers.

Propagation delay skew is dened as the dierence be-

tween the minimum and maximum propaga tion delays,

either t

PLH

or t

PHL

, for any given group of optocouplers

which are operating under the same conditions (i.e., the

same drive current, supply voltage, output load, and op-

erating temperature). As illustrated in Figure 25, if the in-

puts of a group of optocouplers are switched either ON

or OFF at the same time, t

PSK

is the dier ence between

the shortest propagation delay, either t

PLH

or t

PHL

, and the

longest propagation delay, either t

PLH

or t

PHL

As mentioned earlier, t

PSK

can determine the maximum

parallel data transmission rate. Figure 26 is the timing

diagram of a typical parallel data application with both

the clock and the data lines being sent through opto-

couplers.

Table 1. Eects of Common Mode Pulse Direction on Transient I

LED

If |I

| < |I

|, If |I

| > |I

LED I

Current LED I

Current

If dV

/dt Is: then I

Flows: and I

Flows: Is Momentarily: Is Momentarily:

positive (>0) away from LED away from LED increased decreased

anode through C

cathode through C

negative (<0) toward LED toward LED decreased increased

anode through C

cathode through C

Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew

Propagation delay is a gure of merit which describes

how quickly a logic signal propagates through a sys-

tem. The propaga tion delay from low to high (t

PLH

) is the

amount of time required for an input signal to propa-

gate to the output, causing the output to change from

low to high. Similarly, the propagation delay from high

to low (t

PHL

) is the amount of time required for the input

signal to propagate to the output, causing the output to

change from high to low (see Figure 9).

Pulse-width distortion (PWD) results when t

PLH

and t

PHL

dier in value. PWD is dened as the dierence between

PLH

and t

PHL

and often determines the maximum data

rate capability of a transmission system. PWD can be ex-

pressed in percent by dividing the PWD (in ns) by the

minimum pulse width (in ns) being transmitted. Typical-

ly, PWD on the order of 20-30% of the minimum pulse

width is tolerable; the exact gure depends on the par-

ticular appli cation (RS232, RS422, T-1, etc.).

Propagation delay skew, t

PSK

, is an important parameter

to con sider in parallel data applications where synchro-

nization of signals on parallel data lines is a con cern. If

the parallel data is being sent through a group of opto-

820 Ω

74HC00

(OR ANY

OPEN-COLLECTOR/

OPEN-DRAIN

LOGIC GATE)

HCPL-261X

LED

750 Ω

74HC04

(OR ANY

TOTEM-POLE

OUTPUT LOGIC

GATE)

HCPL-261A/261N

1N4148

LED

50%

1.5 V

50%I

PSK

1.5 V

TPHL

TPLH

DATA

PSK

INPUTS

CLOCK

DATA

OUTPUTS

CLOCK

PSK

Figure 25. Illustration of propagation delay skew – t

PSK

Figure 26. Parallel data transmission example.

The gure shows data and clock signals at the inputs and

outputs of the optocouplers. To obtain the maximum

data transmission rate, both edges of the clock signal are

being used to clock the data; if only one edge were used,

the clock signal would need to be twice as fast.

Propagation delay skew repre sents the uncertainty of

where an edge might be after being sent through an op-

tocoupler. Figure 26 shows that there will be uncertainty

in both the data and the clock lines. It is important that

these two areas of uncer tainty not overlap, otherwise

the clock signal might arrive before all of the data out-

puts have settled, or some of the data outputs may start

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AV02-0391EN - April 30, 2013

to change before the clock signal has arrived. From these

considera tions, the absolute minimum pulse width that

can be sent through optocouplers in a parallel applica-

tion is twice t

PSK

. A cautious design should use a slightly

longer pulse width to ensure that any additional uncer-

tainty in the rest of the circuit does not cause a prob-

lem.

The t

PSK

specied optocouplers oer the advantages of

guaran teed specications for propaga tion delays, pulse-

width distortion, and propagation delay skew over the

recommended temperature, input current, and power

supply ranges.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

HCPL-063A

Mfr. #:

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High Speed Optocouplers 10MBd 2Ch 5mA

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