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NCP1219AD65R2G

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NCP1219
http://onsemi.com
13
ON OFF ON
Fault
Figure 26. V
CC
Double Hiccup Operation with a Fault Occurring While the Startup Circuit is Enabled
UVLO
Fault2
DRV
V
CC(reset)
V
CC(on)
V
CC(MIN)
V
CC(hiccup)
An internal supervisory circuit monitors the V
CC
voltage
to prevent the controller from dissipating excessive power
if the V
CC
pin is accidentally grounded. A lower level
current source (I
inhibit
) charges C
CC
from 0 V to V
inhibit
,
typically 0.67 V. Once V
CC
exceeds V
inhibit
, the startup
current source is enabled. This behavior is illustrated in
Figure 27. This slightly increases the total time to charge
V
CC
, but it is generally not noticeable.
Figure 27. Startup Current at Various V
CC
Levels
V
CC
V
CC(on)
V
CC(MIN)
V
inhibit
Startup Current
I
start
I
inhibit
The start−up circuit is rated at a maximum voltage of
500 V. If the device operates in the DSS mode, power
dissipation should be controlled to avoid exceeding the
maximum power dissipation of the controller. If dissipation
on the controller is excessive, a resistor can be placed in
series with the HV pin. This will reduce power dissipation
on the controller and transfer it to the series resistor.
Standby mode losses and normal mode power dissipation
can be reduced by biasing the controller with an auxiliary
winding. The auxiliary winding needs to maintain V
CC
above V
CC(MIN)
once the startup circuit is disabled.
The power dissipation of the controller when operated in
DSS mode, P
DSS
, can be calculated using equation 1, where
I
CC3
is the operating current of the NCP1219 during
switching and V
HV
is the voltage at the HV pin. The HV pin
is most often connected to the bulk capacitor.
P
DSS
+ I
CC3
@ (V
HV
* V
CC
) (eq. 1)
In comparison, the power dissipation when the startup
circuit is disabled and V
CC
is being supplied by the
auxiliary winding is a function of the V
CC
voltage. This is
shown in Equation 2.
P
AUX
+ I
CC3
@ V
CC
(eq. 2)
It is recommended that an external filter capacitor be
placed as close as possible to the V
CC
pin to improve the
noise immunity.
Soft−Start Operation
Figures 28 and 29 show how the soft−start feature is
included in the pulse−width modulation (PWM)
comparator. When the NCP1219 starts up, a soft−start
voltage V
SSTART
begins at 0 V. V
SSTART
increases
gradually from 0 V to 1.0 V in 4.8 ms and stays at 1.0 V
afterward. V
SSTART
is compared with the divided by 3
feedback pin voltage (V
FB
/3). The lesser of V
SSTART
and
(V
FB
/3) becomes the modulation voltage, V
PWM
, in the
PWM duty ratio generation. Initially, (V
FB
/3) is above
1.0 V because the FB pin is brought to V
FB(open)
, typically
3.6 V, by the internal pullup resistor. As a result, V
PWM
is
limited by the soft−start function and slowly ramps up the
duty ratio (and therefore the primary current) for the initial
4.8 ms. This provides a greatly reduced stress on the power
devices during startup.
Figure 28. V
PWM
is the lesser of V
SSTART
and (V
FB
/3)
−
)
V
PWM
V
SSTART
V
FB
/3
01
NCP1219
http://onsemi.com
14
Figure 29. Soft−Start (Time = 0 at V
CC
= V
CC(on)
)
time
time
time
time must be less than t
OVLD
to prevent fault condition
time
1 V
Soft−start voltage, V
SSTART
t
SSTART
1 V
Feedback pin voltage divided by 3, V
FB
/3
t
SSTART
t
SSTART
Drain Current, I
D
1 V
Pulse Width Modulation voltage, V
PWM
Current−Mode Pulse Width Modulation
The NCP1219 is a current−mode, fixed frequency pulse
width modulation controller with ramp compensation. The
PWM block of the NCP1219 is shown in Figure 30. The
DRV signal is enabled by a clock pulse. At this time,
current begins to flow in the power MOSFET and the sense
resistor. A corresponding voltage is generated on the CS
pin of the device, ranging from very low to as high as the
maximum modulation voltage, V
PWM
(maximum of 1 V).
This sets the primary current on a cycle−by−cycle basis.
Equation 3 gives the maximum drain current, I
D(MAX)
,
where R
CS
is the current sense resistor value and V
ILIM
is
the current sense voltage threshold.
I
D(MAX)
+
V
ILIM
R
CS
(eq. 3)
Figure 30. Current−Mode Implementation
LEB
CS
PWM
Output
180 ns
+
−
(1 V max. signal)
Clock
I
ramp(peak)
V
bulk
I
D
R
CS
V
CS
Q
S
80%
max duty
R
V
PWM
I
ramp
Figure 31 shows the timing diagram for the
current−mode pulse width modulation operation. An
internal clock sets the output RS latch, pulling the DRV pin
high. The latch is then reset when the voltage on the CS pin
intersects the modulation voltage, V
PWM
. This generates
the duty ratio of the DRV pulse. The maximum duty ratio
is internally limited to 80% (typical) by the output RS latch.
Figure 31. Current−Mode Timing Diagram
PWM
Output
clock
V
PWM
V
CS
The V
PWM
voltage is the scaled representation of the FB
pin voltage. The scale factor, I
ratio
, is 3. The FB pin voltage
is provided by an external error amplifier, whose output is
a function of the power supply output. An FB signal
between V
skip
and 3 V determines the duty ratio of the
controller output. The FB voltage operates in a closed loop
with the output voltage to regulate the power supply.
It is recommended that an external filter capacitor be
placed as close to the FB pin as possible to improve the
noise immunity.
NCP1219
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15
Ramp Compensation
Ramp compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
continuous conduction mode (CCM) with a duty ratio
greater than 50%. To lower the current loop gain, one
usually injects 50 to 75% of the inductor current down
slope. The NCP1219 generates an internal current ramp
that is synchronized with the clock. This current ramp is
then routed to the CS pin. Figures 32 and 33 depict how the
ramp is generated and utilized. Ramp compensation is
simply formed by placing a resistor, R
ramp
, between the CS
pin and the sense resistor.
Figure 32. Internal Ramp Compensation Current
Source
0
time
80% of period
100% of period
I
ramp(peak)
Ramp current, I
ramp
Figure 33. Inserting a Resistor in Series with the
Current Sense Information Provides Ramp
Compensation
Clock
Oscillator
DRV
CS
Current
Ramp
I
ramp(peak)
R
ramp
R
CS
In order to calculate the value of the ramp compensation
resistor, R
ramp
, the off time primary current slope,
S
off,primary
must be calculated using Equation 4,
S
off,primary
+
(V
out
) V
f
) @
ǒ
N
P
N
S
Ǔ
L
P
(eq. 4)
where V
out
is the converter output voltage, V
f
is the forward
diode drop of the secondary diode, N
P
/N
S
is the primary to
secondary turns ratio, and L
P
is the primary inductance of
the transformer. The value of R
ramp
can be calculated using
Equation 5,
R
ramp
+
ǒ
S
off,primary
R
CS
Ǔ
@ %slope
ǒ
I
ramp(peak)
f
OSC
D
Ǔ
(eq. 5)
where R
CS
is the current sense resistor and %slope is the
percentage of the current downslope to be used for ramp
compensation.
The NCP1219 has a peak ramp compensation current of
100 mA. A frequency of 65 kHz with an 80% maximum
duty ratio corresponds to an 8.1 mA/ms ramp. For a typical
flyback design, let’s assume that the primary inductance is
350 mH, the converter output is 19 V, the V
f
of the output
diode is 1 V and the N
P
:N
S
ratio is 10:1. The off time
primary current slope is given by Equation 6.
(V
out
) V
f
)
ǒ
N
P
N
S
Ǔ
L
P
+ 571
mA
ms
(eq. 6)
When projected over an R
CS
of 0.1 W (for example), this
becomes 57 mV/ms. If we select 50% of the downslope as
the required amount of ramp compensation, then we shall
inject 28.5 mV/ms. Therefore, R
ramp
is simply equal to
Equation 7.
R
ramp
+
28.5
mV
ms
8.1
mA
ms
+ 3.5 kW
(eq. 7)
Ramp compensation greater than 50% of the inductor
down slope can be used if necessary; however,
overcompensating will degrade the transient response of
the system. The addition of ramp compensation also
reduces the total available output power of the system.
Internal Oscillator
The internal oscillator of the NCP1219 provides the
clock signal that sets the DRV signal high and limits the
duty ratio to 80% (typical). The oscillator has a fixed
frequency of 65 kHz or 100 kHz. The NCP1219 employs
frequency jittering to smooth the EMI signature of the
system by spreading the energy of the main switching
component across a range of frequencies. An internal low
frequency oscillator continuously varies the switching
frequency of the controller by ±7.5%. The period of
modulation is 6 ms, typical. Figure 34 illustrates the
oscillator frequency modulation.
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NCP1219AD65R2G

Mfr. #:
Buy NCP1219AD65R2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers ANA PWM CONTROLLER
Lifecycle:
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