NCP1219
http://onsemi.com
16
Figure 34. Oscillator Frequency Modulation
time
Oscillator Frequency
F
OSC
− 7.5%
F
OSC
+ 7.5%
F
OSC
6 ms
Gate Drive
The output drive of the NCP1219 is designed to directly
drive the gate of an n−channel power MOSFET. The DRV
pin is capable of sourcing 500 mA and sinking 800 mA of
drive current. It has typical rise and fall times of 30 ns and
20 ns, respectively, driving a 1 nF capacitive load.
The power dissipation of the output stage while driving
the capacitance of the power MOSFET must be considered
when calculating the NCP1219 power dissipation. The
driver power dissipation can be calculated using
Equation 8,
P
DRV
+ f
OSC
@ Q
G
@ V
CC
(eq. 8)
where Q
G
is the gate charge of the power MOSFET.
External Latch Input
Board level protection functionality is often
incorporated using external circuits to suit a specific
application. An external fault condition can be used to
disable the controller by bringing the voltage on the
Skip/latch pin above the latch threshold, V
latch
(3.9 V
typical). When an external fault condition is detected, the
DRV signal is stopped, and the controller enters low current
operation mode. The external capacitor C
CC
discharges
and V
CC
drops until V
CC(hiccup)
is reached. The high
voltage startup circuit turns on and I
start
charges C
CC
until
V
CC(on)
is reached. V
CC
cycles between V
CC(on)
and
V
CC(hiccup)
until V
CC
reaches V
CC(reset)
. Voltage must be
removed from the HV pin, disabling the startup current and
allowing C
CC
to discharge to V
CC(reset)
. Therefore, the
controller is reset by unplugging the power supply from the
wall to allow V
bulk
to discharge. Figure 35 illustrates the
timing diagram of V
CC
in the latch−off condition.
Figure 35. Latch−off V
CC
Timing Diagram
V
CC(hiccup)
V
CC(on)
Startup current source is
charging the V
CC
capacitor
Startup current source is
off when V
CC
is V
CC(on)
Startup current source turns
on when V
CC
reaches V
CC(hiccup)
time
The external latch feature allows the circuit designers to
implement different kinds of latching protection. Figure 36
shows an example circuit in which a bipolar transistor is
used to pull the Skip/latch pin above the latch threshold.
The R
LIM
value is chosen to prevent the Skip/latch pin from
exceeding the maximum rated voltage. The NCP1219
applications note (AND8393/D) details several simple
circuits to implement overtemperature protection (OTP)
and overvoltage protection (OVP).
Figure 36. Circuit Example of an External
Latch−off Circuit
R
skip
C
skip
R
LIM
V
CC
NCP1219
Skip/latch
FB
GND
CS
VCC
DRV
Fault
output
HV
An internal blanking filter prevents fast voltage spikes
caused by noise from latching the part. However, it is
recommended that an external filter capacitor be placed as
close as possible to the Skip/latch pin to further improve the
noise immunity.
