NCP1219
http://onsemi.com
12
DETAILED OPERATING DESCRIPTION
The NCP1219 is part of a product family of current mode
controllers designed for ac−dc applications requiring low
standby power. The controller operates in skip or burst
mode at light load. Its high integration reduces component
count resulting in a more compact and lower cost power
supply. This device family has 2 options, A and B. Option
A latches where as option B auto restarts after an overload
fault.
The internal high voltage startup circuit with dynamic
self supply (DSS) allows the controller to operate without
an auxiliary supply, simplifying the transformer design.
This feature is particularly useful in applications where the
output voltage varies during operation (e.g. printer
adapters).
Other features found in the NCP1219 are frequency
jittering, adjustable ramp compensation, timer based fault
detection and a dedicated latch input.
High Voltage Startup Circuit
The NCP1219 internal high voltage startup circuit
eliminates the need for external startup components and
provides a faster startup time compared to an external
startup resistor. The startup circuit consists of a constant
current source that supplies current from the HV pin to the
supply capacitor on the V
CC
pin (C
CC
). The HV pin is rated
at 500 V allowing direct connection to the bulk capacitor.
The start−up current (I
start
) is typically 12.8 mA.
The startup current source is disabled once the V
CC
voltage reaches V
CC(on)
, typically 12.7 V. The controller is
then biased by the V
CC
capacitor. The current source is
enabled once the V
CC
voltage decays to its minimum
operating threshold (V
CC(MIN)
) typically 9.9 V. If the
supply current consumption exceeds the startup current,
V
CC
will decay below V
CC(MIN)
. The NCP1219 has an
undervoltage lockout (UVLO) to prevent operation at low
V
CC
levels. The UVLO threshold is typically 9.4 V. The
DRV signal is immediately disabled upon reaching UVLO.
It is re−enabled if V
CC
increases above UVLO before the
50 ms (typical) timer expires. Otherwise, the controller
enters double hiccup mode.
The controller enters a double hiccup mode if an
overload (option B), thermal shutdown, UVLO or latch
fault is detected. A double hiccup fault disables the DRV
signal, sets the controller in a low current mode and allows
V
CC
to discharge to V
CC(hiccup)
, typically 5.7 V. This cycle
is repeated twice to minimize power dissipation in external
components during a fault event. Figures 25 and 26 show
double hiccup mode operation with a fault occurring while
the startup circuit is disabled and enabled, respectively. A
soft−start sequence is initiated the second time V
CC
reaches
V
CC(on)
. If the fault is present or the controller is latched
upon reaching V
CC(on)
, the controller stays in hiccup mode.
During this mode, V
CC
never drops below 4 V, the
controller logic reset level. This prevents latched faults
from being cleared unless power to the controller is
completely removed (i.e. unplugging the supply from the
AC line). There are two options available in the NCP1219,
options A and B. Option A latches off after the overload
timer expires if an overload fault is detected. In this case,
V
CC
cycles between V
CC(on)
and V
CC(hiccup)
without
enabling the DRV signal until the power to the controller
is reset. On the other hand, option B has auto−retry circuitry
allowing the DRV signal to restart after a double hiccup
sequence triggered by an overload condition.
UVLO
Fault1
DRV ON OFF ON
Fault
Figure 25. V
CC
Double Hiccup Operation with a Fault Occurring While the Startup Circuit is Disabled.
V
CC(reset)
V
CC(on)
V
CC(MIN)
V
CC(hiccup)
