NCP1219BD65R2G Datasheet NCP1219AD65R2G, NCP1219BD65R2G, NCP1219AD100R2G | P4-P6

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Table 1. PIN FUNCTION DESCRIPTION

Pin Name Description

1 Skip/latch This pin provides a latch input to permanently disable the device under a fault condition. It also allows the user to

adjust the skip threshold. A resistor between this pin and GND provides noise immunity to the latch input and sets

the skip threshold. The voltage on this pin is determined by the combination of the internal voltage divider and the

external resistor to ground. The default skip threshold is 1.1 V (typical) if no external resistor is used. An internal

clamp prevents the skip level from increasing above 1.3 V if the Skip/latch pin is pulled high to latch the controller.

2 FB The voltage on this pin is proportional to the output load on the converter. An internal resistor divider sets the

voltage on this pin above the regulation threshold (3 V) and an external optocoupler pulls the pin low to achieve

regulation. While the FB voltage is above its regulation threshold, the overload timer is enabled. If the overload

timer expires, the controller enters a double hiccup mode (option B) or is latched (option A) depending on the ver-

sion of the device. The converter enters skip mode if the FB voltage is below the skip threshold.

3 CS A voltage ramp proportional to the primary current is applied to this pin. The maximum current is reached once the

ramp voltage reaches 1 V (typical). A 100 mA (typical) current source provides ramp compensation. The amount of

ramp compensation is adjusted with a series resistor between the CS pin and the current sense resistor.

4 GND Analog ground.

5 DRV Main output of the PWM Controller. DRV has a source resistance of 12.6 W (typical) and a sink resistance of 6.7 W

(typical).

6 VCC Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source

supplies current from the HV pin to this pin. Once the V

voltage reaches V

CC(on)

(12.7 V typical), the current

source turns off and the DRV is enabled. The current source turns on once V

falls to V

CC(min)

(9.9 V typical).

This mode of operation is known as dynamic self supply (DSS).

If the bias current consumption exceeds the startup current, and V

drops 0.5 V (typical) below V

CC(min)

the con-

verter turns off and enters a double hiccup mode. If the V

voltage is below 0.67 V (typical) the startup current is

reduced to 200 mA (typical), reducing power dissipation.

8 HV This is the input of the high voltage startup regulator and connects directly to the bulk voltage. A controlled current

source supplies current from this pin to the V

capacitor, eliminating the need for an external startup resistor. The

charge current is 12.8 mA (typical).

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Table 2. MAXIMUM RATINGS (Notes 1 − 4)

Rating

Symbol Value Unit

HV Voltage V

−0.3 to 500 V

HV Current I

100 mA

Supply Voltage V

−0.3 to 20 V

Supply Current I

100 mA

Skip/latch Voltage V

Skip/latch

−0.3 to 9.5 V

Skip/latch Current I

Skip/latch

100 mA

FB Voltage V

−0.3 to 5.0 V

FB Current I

100 mA

CS Voltage V

−0.3 to 5.0 V

CS Current I

100 mA

DRV Voltage V

DRV

−0.3 to 20 V

DRV Current I

DRV

−500 to 800 mA

Operating Junction Temperature T

–40 to 150 °C

Storage Temperature Range T

stg

–60 to 150 °C

Power Dissipation (T

= 25°C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad)

D Suffix, Plastic Package Case 751U (SOIC−7) (Note 4)

0.92

Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad)

D Suffix, Plastic Package Case 751U (SOIC−7)

Junction to Air, Low conductivity PCB (Note 3)

Junction to Lead, Low conductivity PCB (Note 3)

Junction to Air, High conductivity PCB (Note 4)

Junction to Lead, High conductivity PCB (Note 4)

177

136

°C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Pins 1– 6: Human Body Model 3000 V per JEDEC JESD22−A114−F.

Pins 1– 6: Machine Model Method 300 V per JEDEC JESD22−A115−A.

Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V.

2. This device contains Latch−Up protection and exceeds ±100 mA per JEDEC Standard JESD78.

3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm

of 2 oz copper traces and heat spreading area. As specified for

a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.

4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm

of 2 oz copper traces and heat spreading area. As specified

for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.

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Table 3. ELECTRICAL CHARACTERISTICS (V

= 60 V, V

= 11.3 V, V

= 2 V, V

Skip/latch

= 0 V, V

DRV

= open, C

0.1 mF, for typical values T

= 25°C, for min/max values, T

is –40°C to 125°C, unless otherwise noted)

Characteristics Conditions Symbol Min Typ Max Unit

STARTUP AND SUPPLY CIRCUITS

Supply Voltage

Startup Threshold

Minimum Operating Voltage

Undervoltage Lockout

Double Hiccup Threshold

Logic Reset Voltage

Increasing

Decreasing

CC(on)

CC(MIN)

UVLO

CC(hiccup)

CC(reset)

11.2

9.0

8.4

4.9

–

12.7

9.9

9.4

5.7

4.0

13.8

10.8

10.6

6.3

–

UVLO Filter Delay t

UVLO(delay)

– 50 – ms

Inhibit Threshold Voltage I

inhibit

= 500 mA V

inhibit

0.35 0.67 0.90 V

Inhibit Bias Current V

= 0 V I

inhibit

100 200 350 mA

Minimum Startup Voltage I

start

= 0.5 mA, V

= V

CC(on)

– 0.5 V V

start(min)

– 20 28 V

Startup Current V

= V

(on)

– 0.5 V I

start

5.5 12.8 18.5 mA

Startup Circuit Reverse Current V

= 0 V, V

= 14 V I

HV(reverse)

– – 100 mA

Off−State Leakage Current V

= 500 V, V

= 14 V I

HV(off)

– 12 50 mA

Breakdown Voltage (Note 5) I

= 50 mA V

BR(DS)

500 – – V

Supply Current

Device Disabled/Fault

Device Enabled/No Switching

Device Switching (65 kHz)

Device Switching (100 kHz)

Skip/latch

= 5.2 V, V

= open

Skip/latch

= open, V

= 0 V

Skip/latch

= open, C

DRV

= 1000 pF

Skip/latch

= open, C

DRV

= 1000 pF

CC1

CC2

CC3A

CC3B

–

0.6

1.4

2.2

2.4

0.8

2.1

2.7

3.2

CURRENT SENSE

Current Sense Voltage Threshold Apply voltage step on CS pin V

ILIM

0.95 1.0 1.05 V

Leading Edge Blanking Duration t

LEB

100 184 330 ns

Propagation Delay V

> V

ILIM

to 50% DRV turns off,

DRV

= 1000 pF

delay

– 59 150 ns

Ramp Compensation Peak Current I

ramp(peak)

– 100 – mA

Ramp Compensation Valley Current I

ramp(valley)

– 0 – mA

FEEDBACK INPUT

Open Feedback Voltage V

FB(open)

3.2 3.6 3.9 V

Internal Pull−up Resistance R

– 16.7 – kW

Feedback Pull−up Current V

= 0 V I

141 280 392 mA

Feedback to Current Set Point Ratio I

ratio

– 3.0 –

SOFT−START

Soft−Start Period Measured at 0.9 V

ILIM

SSTART

– 4.8 – ms

OSCILLATOR

Oscillator Frequency

65 kHz Option

100 kHz Option

= 25_C

= −40_C to 85_C

= −40_C to 125_C

= 25_C

= −40_C to 85_C

= −40_C to 125_C

OSC

61.75

–

100

–

68.25

105

107

kHz

Frequency Modulation in

Percentage of f

OSC

– ±7.5 – %

Frequency Modulation Period – 6.0 – ms

Maximum Duty Ratio D 75 80 85 %

5. Guaranteed by the I

HV(off)

test.

6. Guaranteed by design only.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

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NCP1219BD65R2G

NCP1219BD65R2G

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