ESD8008MUTAG

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4
IEC 6100042 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
I
peak
90%
10%
IEC6100042 Waveform
100%
I @ 30 ns
I @ 60 ns
t
P
= 0.7 ns to 1 ns
Figure 5. IEC6100042 Spec
Figure 6. Diagram of ESD Clamping Voltage Test Setup
50 W
50 W
Cable
TVS
Oscilloscope
ESD Gun
The following is taken from Application Note
AND8307/D Characterization of ESD Clamping
Performance.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC6100042 waveform. Since the
IEC6100042 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD8008
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5
Figure 7. Positive TLP IV Curve
Figure 8. Negative TLP IV Curve
TLP CURRENT (A)
V
C
, VOLTAGE (V)
EQUIVALENT V
IEC
(kV)
20
18
16
14
12
10
8
6
4
2
00
8
6
4
2
0201816142468 1210
TLP CURRENT (A)
V
C
, VOLTAGE (V)
EQUIVALENT V
IEC
(kV)
20
0
8
6
4
2
0201816142468 1210
18
16
14
12
10
8
6
4
2
0
NOTE: TLP parameter: Z
0
= 50 W, t
p
= 100 ns, t
r
= 300 ps, averaging window: t
1
= 30 ns to t
2
= 60 ns. V
IEC
is the equivalent voltage
stress level calculated at the secondary peak of the IEC 6100042 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
V
C
= V
HOLD
+ (I
PP
* R
DYN
)
10
10
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (IV) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP IV curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 6100042
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP IV curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
Figure 9. Simplified Schematic of a Typical TLP
System
DUT
L
S
÷
Oscilloscope
Attenuator
10 MW
V
C
V
M
I
M
50 W Coax
Cable
50 W Coax
Cable
Figure 10. Comparison Between 8 kV IEC 6100042 and 8 A and 16 A TLP Waveforms
ESD8008
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6
Figure 11. IEC6100045 8/20 ms Pulse
Waveform
TIME (ms)
50
0
Ipp - PEAK PULSE CURRENT - %Ipp
100
t
r
= rise time to peak value [8 ms]
t
f
= decay time to half value [20 ms]
t
r
t
f
Peak
Value
Half Value
0
Figure 12. Clamping Voltage vs. Peak Pulse Current
(t
p
= 8/20 ms per Figure 11)
8
7
6
5
4
3
2
1
0
087651234
I
pk
(A)
V
pk
(V)
I/OGND
Figure 13. Junction Capacitance; V
R
= 0, f = 500 MHz 10 GHz
Interface
Data Rate
(Gbps)
Fundamental
Frequency (GHz)
3
rd
Harmonic
Frequency (GHz)
ESD8008 Insertion
Loss (dB)
VbyOne HS
Full HD (1920 x 1080p)
240 Hz, 36bit color depth
3.71 1.854 (m1) 5.562 (m3)
m1 = 0.146
m3 = 0.451
Figure 14. ESD8008 Insertion Loss

ESD8008MUTAG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
TVS Diodes / ESD Suppressors LOW CAP ESD PROTECTION
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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