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IDT 89HPES24T3G2 Datasheet
Figure 5 JTAG AC Timing Waveform
Signal Symbol
Reference
Edge
Min Max Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK Tper_16a none 50.0 ns See Figure 5.
Thigh_16a,
Tlow_16a
10.0 25.0 ns
JTAG_TMS
1
,
JTAG_TDI
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b JTAG_TCK rising 2.4 ns
Thld_16b 1.0 ns
JTAG_TDO Tdo_16c JTAG_TCK falling 20 ns
Tdz_16c
2
2.
The values for this symbol were determined by calculation, not by testing.
—20ns
JTAG_TRST_N Tpw_16d
2
none 25.0 ns
Table 12 JTAG AC Timing Characteristics
Tpw_16d
Tdz_16cTdo_16c
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16aTlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRST_N
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IDT 89HPES24T3G2 Datasheet
Recommended Operating Supply Voltages
Absolute Maximum Voltage Rating
Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating voltages
in Table 13. The absolute maximum operating voltages in Table 14 are offered to provide guidelines for voltage excursions outside the recommended
voltage ranges. Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside
the maximum range may adversely affect device functionality and reliability.
Power-Up/Power-Down Sequence
During power supply ramp-up, V
DD
CORE must remain at least 1.0V below V
DD
I/O at all times. There are no other power-up sequence require-
ments for the various operating supply voltages.
The power-down sequence can occur in any order.
Recommended Operating Temperature
Symbol Parameter Minimum Typical Maximum Unit
V
DD
CORE Internal logic supply 0.9 1.0 1.1 V
V
DD
I/O I/O supply except for SerDes LVPECL/CML 3.135 3.3 3.465 V
V
DD
PEA
1
1.
V
DD
PEA and V
DD
PETA should have no more than 25mV
peak-peak
AC power supply noise superimposed on the 1.0V nominal DC
value.
PCI Express Analog Power 0.95 1.0 1.1 V
V
DD
PEHA
2
2.
V
DD
PEHA should have no more than 50mV
peak-peak
AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
V
DD
PETA
1
PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
V
SS
Common ground 0 0 0 V
Table 13 PES24T3G2 Operating Voltages
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply
1.5V 1.5V 4.6V 1.5V 4.6V
Table 14 PES24T3G2 Absolute Maximum Voltage Rating
Grade Temperature
Commercial 0
C to +70C Ambient
Industrial -40
C to +85C Ambient
Table 15 PES24T3G2 Operating Temperatures
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IDT 89HPES24T3G2 Datasheet
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
Number of Active
Lanes per Port
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe Termin-
ation Supply
I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.15V
Typ
3.3V
Max
3.465V
Typ
Power
Max
Power
8/8/8
(Full Swing)
mA 1010 1260 1384 1600 161 176 541 600 3 5
Watts 1.01 1.39 1.38 1.76 0.40 0.48 0.54 0.66 0.010 0.017 3.35 4.31
88/8
(Half Swing)
mA 1010 1260 1190 1376 161 176 281 312 3 5
Watts 1.01 1.39 1.19 1.51 0.40 0.48 0.28 0.34 0.010 0.017 2.89 3.74
Table 16 PES24T3G2 Power Consumption

89HPES24T3G2ZCALG

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC 24-lane, 3-port Gen2 PCIe Switch
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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