89HPES24T3G2ZCALG Datasheet 89HPES24T3G2ZCALG, 89HPES24T3G2ZCALGI, 89HPES24T3G2ZCALG8 | P4-P6

4 of 50 December 16, 2013

IDT 89HPES24T3G2 Datasheet

Pin Description

The following tables list the functions of the pins provided on the PES24T3G2. Some of the functions listed may be multiplexed onto the same pin.

The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)

level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Note: In the PES24T3G2, the two downstream ports are labeled port 2 and port 4.

Signal Type Name/Description

PE0RP[7:0]

PE0RN[7:0]

I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive

pairs for port 0. Port 0 is the upstream port.

PE0TP[7:0]

PE0TN[7:0]

O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 0. Port 0 is the upstream port.

PE2RP[7:0]

PE2RN[7:0]

I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive

pairs for port 2.

PE2TP[7:0]

PE2TN[7:0]

O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 2.

PE4RP[7:0]

PE4RN[7:0]

I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive

pairs for port 4.

PE4TP[7:0]

PE4TN[7:0]

O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 4.

PEREFCLKP

PEREFCLKN

I PCI Express Reference Clock. Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic and on-chip SerDes. The frequency of the dif-

ferential reference clock is determined by the REFCLKM signal.

REFCLKM

REFCLKM is not available in the 19mm package and frequency is set at 100MHz.

I PCI Express Reference Clock Mode Select. This signal selects the fre-

quency of the reference clock input.

0x0 - 100 MHz

0x1 - 125 MHz

This pin should be static and not change following the negation of

PERSTN.

Table 2 PCI Express Interface Pins

Signal Type Name/Description

MSMBADDR[4:1]

I Master SMBus Address. These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize

transfers on the master SMBus.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-

ter SMBus.

SSMBADDR[5,3:1]

I Slave SMBus Address. These pins determine the SMBus address to

which the slave SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

Table 3 SMBus Interface Pins (Part 1 of 2)

5 of 50 December 16, 2013

IDT 89HPES24T3G2 Datasheet

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave

SMBus.

MSMBADDR pins are not available in the 19mm package. Address hardwired to 0x50.

SSMBADDR pins are not available in the 19mm package. Address hardwired to 0x77.

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P2RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 2

GPIO[1] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P4RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 4

GPIO[2] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN0

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 0 input

GPIO[3]

GPIO pins 3, 4, 5, 6 are not available in the 19mm package.

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN1

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 1 input

GPIO[4]

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN2

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 2 input

GPIO[5]

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[6]

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[7] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: GPEN

Alternate function pin type: Output

Alternate function: General Purpose Event (GPE) output

GPIO[8] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[9] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[10] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Table 4 General Purpose I/O Pins

Signal Type Name/Description

Table 3 SMBus Interface Pins (Part 2 of 2)

6 of 50 December 16, 2013

IDT 89HPES24T3G2 Datasheet

Signal Type Name/Description

CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all

downstream ports are using the same clock source as that provided to

downstream devices.This bit is used as the initial value of the Slot Clock

Configuration bit in all of the Link Status Registers for downstream ports.

The value may be overridden by modifying the SCLK bit in each down-

stream port’s PCIELSTS register.

CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the

upstream port is using the same clock source as the upstream device. This

bit is used as the initial value of the Slot Clock Configuration bit in the Link

Status Register for the upstream port. The value may be overridden by

modifying the SCLK bit in the P0_PCIELSTS register.

MSMBSMODE

MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz.

I Master SMBus Slow Mode. The assertion of this pin indicates that the

master SMBus should operate at 100 KHz instead of 400 KHz. This value

may not be overridden.

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside

PES24T3G2 and initiates a PCI Express fundamental reset.

RSTHALT

RSTHALT is not available in the 19mm package.

I Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, PES24T3G2 executes the reset procedure and remains in a reset

state with the Master and Slave SMBuses active. This allows software to

read and write registers internal to the device before normal device opera-

tion begins. The device exits the reset state when the RSTHALT bit is

cleared in the SWCTL register by an SMBus master.

SWMODE[2:0] I Switch Mode. These configuration pins determine the PES24T3G2 switch

operating mode.

0x0 - Normal switch mode

0x1 - Normal switch mode with Serial EEPROM initialization

0x2 - through 0x7 Reserved

These pins should be static and not change following the negation of

PERSTN.

Table 5 System Pins

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is

independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal

is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

Table 6 Test Pins (Part 1 of 2)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P50

89HPES24T3G2ZCALG

Mfr. #:

Buy 89HPES24T3G2ZCALG

Manufacturer:

IDT

Description:

PCI Interface IC 24-lane, 3-port Gen2 PCIe Switch

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

89HPES24T3G2ZCALG

89HPES24T3G2ZCALG

Products related to this Datasheet