XRT83D10 xr
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
10
1.0 SYSTEM DESCRIPTION:
1.1 RECEIVER:
The XRT83D10, a single channel DS1/CEPT Line Interface Unit is a fully integrated transceiver that provides
an electrical interface for DS1 carrier rate (1.544 Mbits/s) or CEPT rate (2.048 Mbits/s) applications.The bipolar
input signals at RTIP and RRING are applied to the peak detector and slicer.Timing recovery is performed by
the Clock and Data Recovery block. EC1,EC2 and EC3 rate control inputs must be set appropriately for DS1 or
CEPT operation. The digital representation of the AMI signals goes to the clock recovery circuit for timing re-
covery before being output to the RPDATA and RNDATA pins. Clock timing recovery of the line interface is ac-
complished by means of a digital PLL scheme which has high input jitter tolerance.
A continuously active (ungapped or unswitched) reference clock must be present at ExCLK to enable the
Timing Generator block. ExCLK must be an independent reference such as an oscillator or system clock for
proper operation. The ExCLK frequency must be 1.544 MHz ± 130 ppm for DS1 operation or 2.048 MHz ± 80
ppm for CEPT operation.
Any data pattern with a minimum long-term 1s density of 12.5% with 15 or fewer consecutive 0s is allowed.
1.1.1 Loss of Signal:
Both digital (DLOS) and analog (ALOS) loss-of-signal detection are used. The analog signal detector uses the
output of the peak detector to determine if a signal is present at RTIP and RRING. If the input amplitude drops
below approximately 0.4 Vp, the analog detector becomes active.Hysteresis is provided in the analog detector
to eliminate ALOS chattering. Either the analog or digital detector sets RLOS "High".
1.2 TRANSMITTER:
The transmitter accepts a clock with positive and negative data (dual-rail NRZ format) and converts the signal
to a balanced bipolar data signal (AMI format). Positive 1s are produced by a positive pulse on device pin TTIP
and negative 1s are produced by a positive pulse on device pin TRING. Binary 0s are converted to null pulses.
All pulse shapes are controlled on-chip according to equalizer control inputs as defined in Table 6 below.
NOTES:
1. * Distance to DSX in feet for 22-Ga. Use maximum loss figures for other cable types.
2. ** dB at 772 kHz.
Transmitter specifications are shown in Figure 6. The DS1 pulse shape template is specified at the DSX and is
illustrated in Figure 6.CEPT transmit waveforms at the device output conform to the template shown in
Figure 7.
T
ABLE 6: EQUALIZER/RATE CONTROL
OPERATION CLOCK RATE
TRANSMITTER
E
QUALIZATION
*
MAXIMUM
C
ABLE LOSS
**
EC1 EC2 EC3
DS1
1.544 MHz
0 ft -131 ft 0.6 0 0 1
131 ft - 262 ft 1.2 0 1 0
262 ft - 393 ft 1.8 0 1 1
393 ft - 524 ft 2.4 1 0 0
524 ft - 655 ft 3.0 1 0 1
CEPT
2.048 MHz
75 Ω -110
120 Ω -111
