XRT83D10IW Datasheet XRT83D10IW, XRT83D10IWTR, XRT83D10IW-F | P4-P6

XRT83D10 xr

REV. 1.0.3 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT

RECEIVER SECTION

PIN #NAME TYPE DESCRIPTION

6RTIP IReceive positive bipolar data Input

5RRING IReceive negative bipolar data Input

20 RCLK O Receive Clock Output

Recovered receive clock for the terminal equipment.

21 RPDATA O Receive positive NRZ data:

Recovered positive data DS1 (1.544Mbits/s) or CEPT (2.048 Mbits/s)

22 RNDATA O Receive negative data

Recovered negative NRZ data DS1 (1.544Mbits/s) or CEPT (2.048 Mbits/s)

12 RLOS O Receive Loss of Signal:

This pin is set "High" if analog loss-of-signal at the receiver input is detected or

if digital loss-of-signal of the recovered data is detected.RLOS will remain

"High" until the loss of signal condition clears.

TRANSMITTER SECTION

PIN #NAME TYPE DESCRIPTION

17 TCLK I Transmit Clock

DS1 Clock Signal. (1.544 MHz ± 130 ppm) or CEPT clock signal (2.048 MHz ±

80 ppm).

18 TPDATA I

Transmit Positive Data

DS1 (1.544 Mbits/s) or CEPT (2.048 Mbits/s) positive bipolar data

19 TNDATA I

Transmit Negative Data

DS1 (1.544 Mbits/s) or CEPT (2.048 Mbits/s) negative bipolar data

23 TTIP O

Transmit Tip Output

Positive bipolar transmit data

25 TRING O

Transmit Differential Ring Output

Negative bipolar transmit data

14 CLKLOS O

Loss of Clock Signal:

This pin is set "High" when either the transmit clock (TCLK) or the clock output

from the jitter attenuator is absent.

xr XRT83D10

SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT

REV. 1.0.3

CONTROL FUNCTION

PIN #NAME TYPE DESCRIPTION

2ICT I In Circuit Testing

When this pin is tied "Low" all output pins are forced to high-impedance state

for in-circuit testing.

NOTE: Internally pulled up.

16 ExCLK I

External Clock Input:

DS1 (1.544 MHz ± 130 ppm) or CEPT E1 (2.048 MHz ± 80 ppm) clock signal is

provided. ExCLK must be an independent clock to guarantee device perfor-

mance for all specifications. This clock must be continuously active (ungapped

or unswitched) and void of jitter for the device to operate properly.

11 TAOS I

Transmit All Ones:

With this pin tied "High", an AMI encoded all "1’s" signal sent to the transmit

output using ExCLK as the timing reference. A remote loop back has higher

priority over TAOS request.

NOTE: Internally pulled down.

9LOOPB I

Loopback control.

LOOPB along with LOOPA is used for selecting different loopbacks.

OTE: Internally Pulled down.

10 LOOPA I

Loopback control.

LOOPB along with LOOPA is used for selecting different loopbacks.

OTE: Internally Pulled down.

13 FOFS O

FIFO Overflow Signal:

This pin is set "High" if the phase jitter of the incoming signal exceeds the toler-

ance of the jitter attenuator’s buffer. This may result in loss of data and Jitter

Attenuator is no longer attenuating jitter.

POWER AND GROUND

PIN #NAME TYPE DESCRIPTION

3 AVDD **** Analog Supply: 5V ± 5% or 3.3V ± 5%

4 AGND **** Analog GND.

24 DVDD **** Digital Supply: 5V ± 5% or 3.3V ± 5%

26 DGND **** Digital GND

LOOPA

Loopback Mode

Normal Operation

Digital

LOOPB

Remote

Local

XRT83D10 xr

REV. 1.0.3 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT

NOTE: Power consumption measurement conditions with 50% 1s on the Transmit and Receive, TA = 25

C, VDD = 5V

OTES:

1. Measured at 772 KHz. 0dB is the Reference to 3.0Vp.

2. Measured at 1024 KHz (both for 75

Ω

and 120

Ω

). 0dB is the Reference to 2.37Vp (75

Ω

) and 3.0Vp (120

Ω

)

TABLE 1: DC ELECTRICAL CHARACTERISTICS

Ta = -40°C to 85°C, Vdd = 5V ± 5% or 3.3V ± 5% unless otherwise specified

PARAMETER SYMBOL MIN TYP MAX UNIT

Input High Voltage V

2.0 5.0 5.5 V

Input Low Voltage V

0.5 0 0.8 V

Output High Voltage @IOH=5mA (See Note)

VDD=5.0v

VDD=3.3v

2.4

VDD

Output Low Voltage @ IOL=5mA (See Note)

VDD=5.0v

VDD=3.3v

0.4

Input Leakage Current (except input pins with pull-up

resistors)

- 0 10 uA

Input Capacitance C

- 5 20 pF

Output Load Capacitance C

- - 20 pF

ELECTRICAL CHARACTERISTICS- POWER SPECIFICATIONS

PARAMETER SYMBOL MIN TYP MAX UNIT

Power Dissipation:

With Jitter Attenuator

DS1 (EC1=0,EC2=1,EC3=1)

CEPT (75 Ω)

CEPT (120 Ω)

275

350

TABLE 2: RECEIVER CHARACTERISTICS

TA = -40°C to 85°C, VDD = 5V± 5% or 3.3V ± 5% Unless otherwise specified

PARAMETER MIN.TYP.MAX UNIT

Receiver Sensitivity

DS1

CEPT

Recovered Clock Jitter Transfer Corner Frequency - 20 kHz

Jitter Attenuator Corner Frequency (-3dB curve) - 3 Hz

Return Loss in E1 (CEPT) Mode

51kHz-102kHz

102kHz-2048kHz

2048kHz-3072kHz

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

XRT83D10IW

Mfr. #:

Buy XRT83D10IW

Manufacturer:

MaxLinear

Description:

Telecom Interface ICs

Lifecycle:

New from this manufacturer.

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XRT83D10IW

XRT83D10IW

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