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PDI1284P11DGG,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 9 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
11. Waveforms
Fig 3. Input An to output Bn or Yn propagation delays
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2.4 V
0.4 V
V
O
t
PLH
t
PHL
V
O
− 1.4 V1.4 V
1.4 V 1.4 Vinput
output
V
M
= 1.5 V.
V
CC
never goes below 3.0 V.
V
OL
and V
OH
are the typical voltage output levels that occur with the output load.
Fig 4. Input Bn, Cn to output An propagation delays
001aai292
V
M
input
output
t
PHL
t
PLH
GND
V
I
V
OH
V
OL
V
M
Measurement data is given in Table 8.
SR is measured for both a LOW-to-HIGH and a HIGH-to-LOW transition.
Fig 5. Slew rate on B/Y side
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t1
1.9 V
2.4 V
0.4 V
2.4 V
0.9 V
0.4 V
output
input
t2 t1 t2
Table 8. Slew rate measurements
t
r
t
f
t
W
R
L
V
O
transition (see Figure 8)
Rising Falling
3 ns 3 ns 150 ns < t
W
< 10 µs62Ω from V
O
= 0.4 V to V
O
= 0.9 V from V
O
= 2.4 V to V
O
= 1.9 V
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 10 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
Test circuit is shown in Figure 7.
Measurement points are given in Table 9.
V
OL
and V
OH
are the typical voltage output levels that occur with the output load.
Fig 6. Enable and disable times
001aai294
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
HD to B
DIR to B
DIR to A
V
I
V
OL
V
OH
V
CC
V
M
V
M
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
Test conditions are given in Table 9.
Fig 7. Test circuit for measuring enable and disable times
V
EXT
V
CC
V
I
V
O
mna616
DUT
C
L
R
T
R
L
R
L
G
Table 9. Test data for test circuit measuring enable disable times Bn to An
Parameter V
CC
Input Output V
EXT
V
I
V
M
V
M
V
X
V
Y
t
PZH
, t
PHZ
t
PZL
, t
PLZ
DIR to Bn, An;
OEA to An
< 2.7 V V
CC
1.5 V 1.5 V V
OL
± 0.3 V V
OH
− 0.3 V GND 2V
CC
2.7 V to 3.6 V 2.7 V 1.5 V 1.5 V V
OL
± 0.3 V V
OH
− 0.3 V GND 2V
CC
HD to Yn or Bn;
HD to PHLO
< 2.7 V V
CC
1.5 V 1.5 V - V
OH
− 0.3 V open -
2.7 V to 3.6 V 2.7 V 1.5 V 1.5 V - V
OH
− 0.3 V open -
PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 11 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
a. Input pulse definition
b. Test circuit
C
L
= load capacitance includes jig and probe capacitance.
R
L
= load resistance.
R
T
= termination resistance should be equal to the output impedance of the pulse generator.
Test conditions for propagation delays are given in Table 10, test conditions for slew rate are given in Table 8
Fig 8. Test circuit for An, Bn and Yn outputs; slew rate B/Y side
001aai298
V
M
V
M
t
W
t
W
10 %
90 % 90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 % 10 %
t
f
t
r
t
r
t
f
R
L
C
L
001aai296
V
CC
V
I
V
O
V
EXT
GND
R
T
DUT
G
Table 10. Test conditions for An, Bn and Yn outputs
Output V
I
V
M
Repetition
rate
t
W
t
r
t
f
Switch position
t
PLH
, t
PZH
t
PHL
, t
PHZ
An 3.0 V 1.5 V 1 MHz 500 ns 3ns 3ns GND GND
Bn, Yn 3.0 V 1.5 V 1 MHz 500 ns
3ns 3ns GND V
EXT
= 2.8 V
I
O
is measured by forcing 0.5V
CC
on the output. The output impedance can then be calculated as R
o
= 0.5V
CC
/ |I
O
|.
Fig 9. Output impedance
001aai299
V
CC
/ 2
DUT
I
O
V
CC
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PDI1284P11DGG,518

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Buy PDI1284P11DGG,518
Manufacturer:
Nexperia
Description:
IC TXRX/BUFFER PARALLEL 48-TSSOP
Lifecycle:
New from this manufacturer.
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