PDI1284P11_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 25 August 2008 5 of 16
NXP Semiconductors
PDI1284P11
3.3 V parallel interface transceiver/buffer
[1] Pin with pull-up resistor to load cable.
6. Functional description
6.1 Function selection
[1] An = side driving internal IC;
Bn = side driving external cable (bidirectional);
Cn = side receiving control signals from external cable;
H = HIGH voltage level;
L = LOW voltage level;
OC = Open Collector;
X = don’t care (control signals in);
Yn = side driving external cable (unidirectional);
Z = high impedance (high-Z) or 3-state;
TP = totem pole output;
RP = resistive pull-up: 1.4 kΩ (nominal) on B/Y/C cable side and V
CC
. However, while a B/Y side output is LOW as driven by a LOW
signal on the A side, that particular B/Y side resistor is switched off to stop current drain from V
CC
through it.
[2] When DIR = L and OEA = H, the output signal is isolated from the input signal. Signals B1 to B8 maintain a resistive pull-up of 1.4 kΩ on
the input for this mode.
HLHO 24 host logic high output (cable)
HLHI 25 host logic high input (cable)
PLHO 30 peripheral logic high output (cable)
V
CC(B)
31, 42 supply voltage B (cable side 3 V/5 V)
OEA 34 A side output enable input (active LOW)
DIR 48 direction selection input
Table 2. Pin description
…continued
Symbol Pin Description
Table 3. Function table
[1]
DIR OEA HD Input Output Output type
X X X C14 to C17 A14 to A17 TP
X X X HLHI HLHO TP
X X L A9 to A13 Y9 to Y13 RP
X X H A9 to A13 Y9 to Y13 TP
X X L PLHI PLHO OC
X X H PLHI PLHO TP
H X L A1 to A8 B1 to B8 RP
H X H A1 to A8 B1 to B8 TP
L L X B1 to B8 A1 to A8 TP
L H X - A1 to A8 Z
[2]
L H X B1 to B8 - RP
[2]
