Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. B
04/22/2015
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specication and its products at any time without notice. ISSI assumes no liability arising
out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specication before relying on any published informa-
tion and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of
the life support system or to signicantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its
satisfaction, that:
a.) the risk of injury or damage has been minimized;
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IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
1M x 16 HIGH-SPEED LOW POWER
ASYNCHRONOUS CMOS STATIC RAM
APRIL 2015
FEATURES
• High-speedaccesstimes:
25,35ns
• High-performance,low-powerCMOSprocess
• Multiplecenterpowerandgroundpinsforgreater
noiseimmunity
• EasymemoryexpansionwithCS1andOEoptions
• CS1power-down
• Fullystaticoperation:noclockorrefresh
required
• TTLcompatibleinputsandoutputs
• Singlepowersupply
Vdd1.65Vto2.2V(IS62WV102416ALL)
speed=35nsforVdd1.65Vto2.2V
Vdd2.4Vto3.6V(IS62/65WV102416BLL)
speed=25nsforVdd2.4Vto3.6V
• Packagesavailable:
–
48-ballminiBGA(9mmx11mm)
–48-pinTSOP(TypeI)
• IndustrialandAutomotiveTemperatureSupport
• Lead-freeavailable
• Datacontrolforupperandlowerbytes
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
TheISSIIS62WV102416ALL/BLLandIS65WV102416BLL
arehigh-speed,16M-bitstaticRAMsorganizedas1024K
wordsby16bits.ItisfabricatedusingISSI'shigh-perfor-
mance CMOS technology. This highly reliable process
coupledwithinnovativecircuitdesigntechniques,yields
high-performanceandlowpowerconsumptiondevices.
WhenCS1isHIGH(deselected)orwhenCS2isLOW
(deselected)orwhen CS1isLOW,CS2isHIGHandboth
LBandUBareHIGH,thedeviceassumesastandbymode
atwhichthepowerdissipationcanbereduceddownwith
CMOSinputlevels.
EasymemoryexpansionisprovidedbyusingChipEnable
andOutputEnableinputs.TheactiveLOWWriteEnable
(WE)controlsbothwritingandreadingofthememory.A
databyteallowsUpperByte(UB)andLowerByte(LB)
access.
Thedevice is packagedin theJEDECstandard 48-pin
TSOPTypeIand48-pinMiniBGA(9mmx11mm).
A0-A19
CS1
OE
WE
1024K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB