Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. B
04/22/2015
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
Notes:
1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesontheCS1,CS2andWEinputsandatleastoneofthe
LBandUBinputsbeingintheLOWstate.
2. WRITE=(CS1)[(LB)=(UB)](WE).
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(CS1Controlled,OE=HIGHorLOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
LB, UB
t
PWB
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(OverOperatingRange)
25ns
35 ns
Symbol Parameter Min. Max. Min. Max. Unit
twC WriteCycleTime 25 — 35 — ns
tsCs1/tsCs2 CS1/CS2toWriteEnd 18 — 25 — ns
taw AddressSetupTimetoWriteEnd 15 — 25 — ns
tHa AddressHoldfromWriteEnd 0 — 0 — ns
tsa AddressSetupTime 0 — 0 — ns
tPwb LB, UBValidtoEndofWrite 18 — 25 — ns
tPwe
(4)
WEPulseWidth 18 — 30 — ns
tsd DataSetuptoWriteEnd 12 — 15 — ns
tHd DataHoldfromWriteEnd 0 — 0 — ns
tHzwe
(3)
WELOWtoHigh-ZOutput — 12 — 20 ns
tLzwe
(3)
WEHIGHtoLow-ZOutput 5 — 5 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4toVdd-0.2V/0.4V
toV
dd-0.3VandoutputloadingspeciedinFigure1.
2.
Theinternalwritetimeisdenedbytheoverlapof CS1 LOW,CS2HIGHandUBorLB,andWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,but
anyonecangoinactiveto
terminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatesthe
write.
3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
4.t
Pwe
> tHzwe + tsd whenOEisLOW.