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IS62WV102416BLL-25TLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
04/22/2015
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z
DATA VALID
t
HZCS1/
t
HZCS1
ADDRESS
OE
CS1
s
CS2
s
DOUT
LB
s
,
UB
s
t
HZB
t
BA
t
LZB
AC WAVEFORMS
READ CYCLE NO. 2
(1,3)
(CS1, CS2, OE,ANDUB/LB Controlled)
Notes:
1. WEisHIGHforaReadCycle.
2. Thedeviceiscontinuouslyselected.OE, CS1, UB,orLB=
ViL. Cs2=WE=ViH.
3. AddressisvalidpriortoorcoincidentwithCS1LOWtransition.
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. B
04/22/2015
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
Notes:
1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesontheCS1,CS2andWEinputsandatleastoneofthe
LBandUBinputsbeingintheLOWstate.
2. WRITE=(CS1)[(LB)=(UB)](WE).
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(CS1Controlled,OE=HIGHorLOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
LB, UB
t
PWB
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(OverOperatingRange)
25ns
35 ns
Symbol Parameter Min. Max. Min. Max. Unit
twC WriteCycleTime 25 — 35 —  ns
tsCs1/tsCs2 CS1/CS2toWriteEnd 18 — 25 —  ns
taw AddressSetupTimetoWriteEnd 15 — 25 —  ns
tHa AddressHoldfromWriteEnd 0 — 0 —  ns
tsa AddressSetupTime 0 — 0 —  ns
tPwb LB, UBValidtoEndofWrite 18 — 25 —  ns
tPwe
(4)
WEPulseWidth 18 — 30 —  ns
tsd DataSetuptoWriteEnd 12 — 15 —  ns
tHd DataHoldfromWriteEnd 0 — 0 —  ns
tHzwe
(3)
WELOWtoHigh-ZOutput — 12 — 20  ns
tLzwe
(3)
WEHIGHtoLow-ZOutput 5 — 5 —  ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4toVdd-0.2V/0.4V
toV
dd-0.3VandoutputloadingspeciedinFigure1.
2.
Theinternalwritetimeisdenedbytheoverlapof CS1 LOW,CS2HIGHandUBorLB,andWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,but
anyonecangoinactiveto
terminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatesthe
write.
3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
4.t
Pwe
> tHzwe + tsd whenOEisLOW.
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
04/22/2015
IS62WV102416ALL
IS62WV102416BLL
IS65WV102416BLL
WRITE CYCLE NO. 2 (WEControlled:OEisHIGHDuringWriteCycle)
WRITE CYCLE NO. 3 (WEControlled:OEisLOWDuringWriteCycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
tSCS1
tSCS2
tAW
tHA
t PWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
DATA-IN VALID
DATA UNDEFINED
t
WC
tSCS1
tSCS2
tAW
tHA
tPWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

IS62WV102416BLL-25TLI

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ISSI
Description:
SRAM 16M (1Mx16) 25ns Async SRAM
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