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CY28411ZXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
CY28411
......................Document #: 38-07594 Rev. *B Page 13 of 18
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
V
DD
Core Supply Voltage –0.5 4.6 V
V
DD_A
Analog Supply Voltage –0.5 4.6 V
V
IN
Input Voltage Relative to V
SS
–0.5 V
DD
+ 0.5 VDC
T
S
Temperature, Storage Non-functional –65 150 °C
T
A
Temperature, Operating Ambient Functional 0 85 °C
T
J
Temperature, Junction Functional – 150 °C
Ø
JC
Dissipation, Junction to Case
(Mil-Spec 883E Method 1012.1)
SSOP 39.56 °C/W
TSSOP 20.62
Ø
JA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
SSOP 45.29 °C/W
TSSOP 62.26
ESD
HBM
ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V
UL-94 Flammability Rating At 1/8 in. V–0
MSL Moisture Sensitivity Level 1
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.
DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VDD_A
,
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48,
VDD_CPU
3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
V
ILI2C
Input Low Voltage SDATA, SCLK – 1.0 V
V
IHI2C
Input High Voltage SDATA, SCLK 2.2 – V
V
IL_FS
FS_A/FS_B Input Low Voltage V
SS
– 0.3 0.35 V
V
IH_FS
FS_A/FS_B Input High Voltage 0.7 V
DD
+ 0.5 V
V
ILFS_C
FS_C Low Range 0 0.35 V
V
IMFS_C
FS_C Mid Range 0.7 1.7 V
V
IH FS_C
FS_C High Range 2.1 V
DD
V
V
IL
3.3V Input Low Voltage V
SS
– 0.5 0.8 V
V
IH
3.3V Input High Voltage 2.0 V
DD
+ 0.5 V
I
IL
Input Low Leakage Current except internal pull-up resistors, 0 < V
IN
< V
DD
–5 – A
I
IH
Input High Leakage Current except internal pull-down resistors, 0 < V
IN
< V
DD
–5A
V
OL
3.3V Output Low Voltage I
OL
= 1 mA – 0.4 V
V
OH
3.3V Output High Voltage I
OH
= –1 mA 2.4 – V
I
OZ
High-impedance Output Current –10 10 A
C
IN
Input Pin Capacitance 2 5 pF
C
OUT
Output Pin Capacitance 3 6 pF
L
IN
Pin Inductance –7nH
V
XIH
Xin High Voltage 0.7V
DD
V
DD
V
V
XIL
Xin Low Voltage 00.3V
DD
V
I
DD3.3V
Dynamic Supply Current At max. load and freq. per Figure 14 –380mA
I
PD3.3V
Power-down Supply Current PD asserted, Outputs driven – 70 mA
I
PD3.3V
Power-down Supply Current PD asserted, Outputs Hi-Z – 12 mA
CY28411
......................Document #: 38-07594 Rev. *B Page 14 of 18
AC Electrical Specifications
Parameter Description Condition Min. Max. Unit
Crystal
T
DC
XIN Duty Cycle The device will operate reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
47.5 52.5 %
T
PERIOD
XIN Period When XIN is driven from an external
clock source
69.841 71.0 ns
T
R
/ T
F
XIN Rise and Fall Times Measured between 0.3V
DD
and 0.7V
DD
–10.0ns
T
CCJ
XIN Cycle to Cycle Jitter As an average over 1-s duration – 500 ps
L
ACC
Long-term Accuracy Over 150 ms – 300 ppm
CPU at 0.7V
T
DC
CPUT and CPUC Duty Cycle Measured at crossing point V
OX
45 55 %
T
PERIOD
100-MHz CPUT and CPUC Period Measured at crossing point V
OX
9.997001 10.00300 ns
T
PERIOD
133-MHz CPUT and CPUC Period Measured at crossing point V
OX
7.497751 7.502251 ns
T
PERIODSS
100-MHz CPUT and CPUC Period, SSC Measured at crossing point V
OX
9.997001 10.05327 ns
T
PERIODSS
133-MHz CPUT and CPUC Period, SSC Measured at crossing point V
OX
7.497751 7.539950 ns
T
PERIODAbs
100-MHz CPUT and CPUC Absolute
period
Measured at crossing point V
OX
9.912001 10.08800 ns
T
PERIODAbs
133-MHz CPUT and CPUC Absolute
period
Measured at crossing point V
OX
7.412751 7.587251 ns
T
PERIODSSAbs
100-MHz CPUT and CPUC Absolute
period, SSC
Measured at crossing point V
OX
9.912001 10.13827 ns
T
PERIODSSAbs
133-MHz CPUT and CPUC Absolute
period, SSC
Measured at crossing point V
OX
7.412751 7.624950 ns
T
CCJ
CPUT/C Cycle to Cycle Jitter Measured at crossing point V
OX
–125ps
T
CCJ2
CPU2_ITP Cycle to Cycle Jitter Measured at crossing point V
OX
–125ps
T
SKEW2
CPU2_ITP to CPU0 Clock Skew Measured at crossing point V
OX
–150ps
T
R
/ T
F
CPUT and CPUC Rise and Fall Times Measured from V
OL
= 0.175 to V
OH
=
0.525V
175 700 ps
T
RFM
Rise/Fall Matching Determined as a fraction of 2*(T
R
–
T
F
)/(T
R
+ T
F
)
–20%
T
R
Rise Time Variation – 125 ps
T
F
Fall Time Variation – 125 ps
V
HIGH
Voltage High Math averages Figure 14 660 850 mV
V
LOW
Voltage Low Math averages Figure 14 –150 – mV
V
OX
Crossing Point Voltage at 0.7V Swing 250 550 mV
V
OVS
Maximum Overshoot Voltage – V
HIGH
+ 0.3 V
V
UDS
Minimum Undershoot Voltage –0.3 – V
V
RB
Ring Back Voltage See Figure 14. Measure SE – 0.2 V
SRC
T
DC
SRCT and SRCC Duty Cycle Measured at crossing point V
OX
45 55 %
T
PERIOD
100-MHz SRCT and SRCC Period Measured at crossing point V
OX
9.997001 10.00300 ns
T
PERIODSS
100-MHz SRCT and SRCC Period, SSC Measured at crossing point V
OX
9.997001 10.05327 ns
T
PERIODAbs
100-MHz SRCT and SRCC Absolute
Period
Measured at crossing point V
OX
10.12800 9.872001 ns
T
PERIODSSAbs
100-MHz SRCT and SRCC Absolute
Period, SSC
Measured at crossing point V
OX
9.872001 10.17827 ns
T
SKEW
Any SRCT/C to SRCT/C Clock Skew Measured at crossing point V
OX
–100ps
CY28411
......................Document #: 38-07594 Rev. *B Page 15 of 18
T
CCJ
SRCT/C Cycle to Cycle Jitter Measured at crossing point V
OX
–125ps
L
ACC
SRCT/C Long Term Accuracy Measured at crossing point V
OX
– 300 ppm
T
R
/ T
F
SRCT and SRCC Rise and Fall Times Measured from V
OL
= 0.175 to V
OH
=
0.525V
175 700 ps
T
RFM
Rise/Fall Matching Determined as a fraction of 2*(T
R
–
T
F
)/(T
R
+ T
F
)
–20%
T
R
Rise TimeVariation – 125 ps
T
F
Fall Time Variation – 125 ps
V
HIGH
Voltage High Math averages Figure 14 660 850 mV
V
LOW
Voltage Low Math averages Figure 14 –150 – mV
V
OX
Crossing Point Voltage at 0.7V Swing 250 550 mV
V
OVS
Maximum Overshoot Voltage
–
V
HIGH
+
0.3
V
V
UDS
Minimum Undershoot Voltage –0.3 – V
V
RB
Ring Back Voltage See Figure 14. Measure SE – 0.2 V
PCI/PCIF
T
DC
PCI Duty Cycle Measurement at 1.5V 45 55 %
T
PERIOD
Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99100 30.00900 ns
T
PERIODSS
Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.9910 30.15980 ns
T
PERIODAbs
Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.49100 30.50900 ns
T
PERIODSSAbs
Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.49100 30.65980 ns
T
HIGH
PCIF and PCI high time Measurement at 2.4V 12.0 – ns
T
LOW
PCIF and PCI low time Measurement at 0.4V 12.0 – ns
T
R
/ T
F
PCIF and PCI rise and fall times Measured between 0.8V and 2.0V 0.5 2.0 ns
T
SKEW
Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 500 ps
T
CCJ
PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 500 ps
DOT
T
DC
DOT96T and DOT96C Duty Cycle Measured at crossing point V
OX
45 55 %
T
PERIOD
DOT96T and DOT96C Period Measured at crossing point V
OX
10.41354 10.41979 ns
T
PERIODAbs
DOT96T and DOT96C Absolute Period Measured at crossing point V
OX
10.16354 10.66979 ns
T
CCJ
DOT96T/C Cycle to Cycle Jitter Measured at crossing point V
OX
–250ps
L
ACC
DOT96T/C Long Term Accuracy Measured at crossing point V
OX
– 100 ppm
T
R
/ T
F
DOT96T and DOT96C Rise and Fall
Times
Measured from V
OL
= 0.175 to V
OH
=
0.525V
175 700 ps
T
RFM
Rise/Fall Matching Determined as a fraction of 2*(T
R
–
T
F
)/(T
R
+ T
F
)
–20%
T
R
Rise Time Variation – 125 ps
T
F
Fall Time Variation – 125 ps
V
HIGH
Voltage High Math averages Figure 14 660 850 mV
V
LOW
Voltage Low Math averages Figure 14 –150 – mV
V
OX
Crossing Point Voltage at 0.7V Swing 250 550 mV
V
OVS
Maximum Overshoot Voltage – V
HIGH
+ 0.3 V
V
UDS
Minimum Undershoot Voltage –0.3 – V
V
RB
Ring Back Voltage See Figure 14. Measure SE – 0.2 V
USB
T
DC
Duty Cycle Measurement at 1.5V 45 55 %
AC Electrical Specifications (continued)
Parameter Description Condition Min. Max. Unit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CY28411ZXC

Mfr. #:
Buy CY28411ZXC
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products System Clock for Intel Sonoma & Alviso Chipsets (CK410m)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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