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CY28411ZXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
CY28411
........................Document #: 38-07594 Rev. *B Page 7 of 18
Crystal Recommendations
The CY28411 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28411 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Byte 6: Control Register 6
Bit @Pup Name Description
7 0 REF/N or Hi-Z Select
0 = Hi-Z, 1 = REF/N Clock
6 0 Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Hi-Z mode,
5 0 Reserved Reserved, Set = 0
4 1 REF REF Output Drive Strength
0 = Low, 1 = High
3 1 PCIF, SRC, PCI SW PCI_STP Function
0=SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2 Externally
selected
CPUT/C FS_C Reflects the value of the FS_C pin sampled on power up
0 = FS_C was low during VTT_PWRGD# assertion
1 Externally
selected
CPUT/C FS_B Reflects the value of the FS_B pin sampled on power up
0 = FS_B was low during VTT_PWRGD# assertion
0 Externally
selected
CPUT/C FS_A Reflects the value of the FS_A pin sampled on power up
0 = FS_A was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit @Pup Name Description
7 0 Revision Code Bit 3 Revision Code Bit 3
6 0 Revision Code Bit 2 Revision Code Bit 2
5 0 Revision Code Bit 1 Revision Code Bit 1
4 1 Revision Code Bit 0 Revision Code Bit 0
3 1 Vendor ID Bit 3 Vendor ID Bit 3
2 0 Vendor ID Bit 2 Vendor ID Bit 2
1 0 Vendor ID Bit 1 Vendor ID Bit 1
0 0 Vendor ID Bit 0 Vendor ID Bit 0
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz AT Parallel 20 pF 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm
CY28411
........................Document #: 38-07594 Rev. *B Page 8 of 18
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
Figure 1. Crystal Capacitive Clarification
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
CY28411
........................Document #: 38-07594 Rev. *B Page 9 of 18
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual function pin. During initial
power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active high input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted high, all clocks need to be driven
to a low value and held prior to turning off the VCOs and the
crystal oscillator.
PD (Power-down) – Assertion
When PD is sampled high by two consecutive rising edges of
CPUC, all single-ended outputs will be held low on their next
high to low transition and differential clocks must held high or
Hi-Zd (depending on the state of the control register drive
mode bit) on the next diff clock# high to low transition within
four clock periods. When the SMBus PD drive mode bit corre-
sponding to the differential (CPU, SRC, and DOT) clock output
of interest is programmed to ‘0’, the clock output are held with
“Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tri-state.
If the control register PD drive mode bit corresponding to the
output of interest is programmed to “1”, then both the “Diff
clock” and the “Diff clock#” are tristate. Note the example
below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all
differential outputs. This diagram and description is applicable
to valid CPU frequencies 100,133,166,200,266,333 and
400MHz. In the event that PD mode is desired as the initial
power-on state, PD must be asserted high in less than 10 uS
after asserting Vtt_PwrGd#.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 s of PD deassertion to a voltage greater than 200
mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
Figure 3. Power-down Assertion Timing Waveform
PD
USB, 48MHz
DOT96T
DOT96C
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
Figure 4. Power-down Deassertion Timing Waveform
DOT96C
PD
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
USB, 48MHz
DOT96T
SRCT 100MHz
Tstable
<1.8nS
PCI, 33MHz
REF
Tdrive_PWRDN#
<300S, >200mV
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CY28411ZXC

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Buy CY28411ZXC
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products System Clock for Intel Sonoma & Alviso Chipsets (CK410m)
Lifecycle:
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