13
LTC3709
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Both top and bottom MOSFETs have I
2
R losses and the top
MOSFET includes an additional term for transition losses,
which are the largest at maximum input voltages. The
bottom MOSFET losses are the greatest when the bottom
duty cycle is near 100%, during a short circuit or at high
input voltage. A much smaller and much lower input
capacitance MOSFET should be used for the top MOSFET
in applications that have an output voltage that is less than
1/3 of the input voltage. In applications where V
IN
>> V
OUT
,
the top MOSFETs’ “on” resistance is normally less impor-
tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac-
turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
input capacitance for the main switch application in switch-
ing regulators.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage.
The operating frequency of LTC3709 applications is deter-
mined implicitly by the one-shot timer that controls the on
time, t
ON
, of the top MOSFET switch. The on-time is set by
the current into the I
ON
pin according to:
t
I
pF
ON
ION
=
()
07
30
.
Tying a resistor from V
IN
to the I
ON
pin yields an on-time
inversely proportional to V
IN
. For a down converter, this
results in approximately constant frequency operation as
the input supply varies:
f
V
RpF
OUT
ON
=
(
)
(
)
07 30.•
Per Phase
PLL and Frequency Synchronization
In the LTC3709, there are two on-chip phase-lock loops
(PLLs). One of the PLLs is used to achieve frequency
locking and phase separation between the two channels
while the second PLL is for locking onto an external clock.
Since the LTC3709 is a constant on-time architecture, the
error signal generated by the phase detector of the PLL is
used to vary the on-time to achieve frequency locking and
180° phase separation.
The synchronization is set up in a “daisy chain” manner
whereby channel 2’s on-time will be varied with respect to
channel 1. If an external clock is present, then channel 1’s
on-time will be varied and channel 2 will follow suit. Both
PLLs are set up with the same capture range and the fre-
quency range that the LTC3709 can be externally synchro-
nized to is between 2 • f
C
and 0.5 • f
C
, where f
C
is the initial
frequency setting of the two channels. It is advisable to set
initial frequency as close to external frequency as possible.
A limitation of both PLLs is when the on-time is close to the
minimum (100ns). In this situation, the PLL will not be
able to synchronize up in frequency.
To ensure proper operation of the internal phase-lock loop
when no external clock is applied to the FCB pin, the
INTLPF pin may need to be pulled down while the output
voltage is ramping up. One way to do this is to connect the
anode of a silicon diode to the INTLPF pin and its cathode
to the PGOOD pin and connect a pull-up resistor between
the PGOOD pin and V
CC
. Refer to Figure 9 for an example.
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple current:
=
I
V
fL
V
V
L
OUT OUT
IN
1
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
14
LTC3709
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In the Figure 2 graph, the local maximum input RMS
capacitor currents are reached when:
V
V
k
OUT
IN
==
21
4
where k 1, 2
These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that ripple current ratings from capacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to derate the capacitor. Several
capacitors may also be paralleled to meet size or height
requirements in the design. Always consult the capacitor
manufacturer if there is any question.
It is important to note that the efficiency loss is propor-
tional to the input RMS current squared and therefore a
2-stage implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the re-
duction of the input ripple current in a 2-phase system. The
required amount of input capacitance is further reduced by
the factor 2 due to the effective increase in the frequency
of the current pulses.
Figure 2. RMS Input Current Comparison
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
3709 F02
RMS INPUT RIPPLE CURRNET
DC LOAD CURRENT
2-PHASE
1-PHASE
A reasonable starting point is to choose a ripple current
that is about 40% of I
OUT(MAX)
/2. Note that the largest
ripple current occurs at the highest V
IN
. To guarantee that
ripple current does not exceed a specified maximum, the
inductance should be chosen according to:
L
V
fI
V
V
OUT
L MAX
OUT
IN MAX
=
() ()
1
Once the value for L is known, the inductors must be
selected (based on the RMS saturation current ratings). A
variety of inductors designed for high current, low voltage
applications are available from manufacturers such as
Sumida, Toko and Panasonic.
Schottky Diode Selection
The Schottky diodes conduct during the dead time be-
tween the conduction of the power MOSFET switches. It is
intended to prevent the body diode of the bottom MOSFET
from turning on and storing charge during the dead time,
which causes a modest (about 1%) efficiency loss. The
diode can be rated for about one-half to one-fifth of the full
load current since it is on for only a fraction of the duty
cycle. In order for the diode to be effective, the inductance
between the diode and the bottom MOSFET must be as
small as possible, mandating that these components be
placed adjacently. The diode can be omitted if the effi-
ciency loss is tolerable.
C
IN
and C
OUT
Selection
In continuous mode, the current of each top N-channel
MOSFET is a square wave of duty cycle V
OUT
/V
IN
. A low
ESR input capacitor sized for the maximum RMS current
must be used. The details of a close form equation can be
found in Application Note 77. Figure 2 shows the input
capacitor ripple current for a 2-phase configuration with
the output voltage fixed and input voltage varied. The input
ripple current is normalized against the DC output current.
The graph can be used in place of tedious calculations. The
minimum input ripple current can be achieved when the
input voltage is twice the output voltage.
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LTC3709
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The selection of C
OUT
is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The output ripple V
OUT
is approximately bounded by:
∆∆V I ESR
fC
OUT L
OUT
+
1
8
Since I
L
increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long-
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. High performance
through-hole capacitors may also be used, but an addi-
tional ceramic capacitor in parallel is recommended to
reduce the effect of their lead inductance.
Top MOSFET Driver Supply (C
B
, D
B
)
An external bootstrap capacitor C
B
connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode D
B
from DRV
CC
when the switch node is low. Note that the average voltage
across C
B
is approximately DRV
CC
. When the top MOSFET
turns on, the switch node rises to V
IN
and the BOOST pin
rises to approximately V
IN
+ DRV
CC
. The boost capacitor
needs to store about 100 times the gate charge required by
the top MOSFET. In most applications 0.1µF to 0.47µF is
adequate.
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Discontinuous Mode Operation and FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin to V
CC
enables discontinuous operation where the
bottom MOSFET turns off when inductor current reverses.
The load current at which inductor current reverses and
discontinuous operation begins depends on the amplitude
of the inductor ripple current. The ripple current depends
on the choice of inductor value and operating frequency as
well as the input and output voltages.
Tying the FCB pin to ground forces continuous synchro-
nous operation, allowing current to reverse at light loads
and maintaining high frequency operation.
Besides providing a logic input to force continuous opera-
tion, the FCB pin acts as the input for external clock syn-
chronization. Upon detecting a TTL level clock and the fre-
quency is higher than the minimum allowable, channel 1
will lock on to this external clock. This will be followed by
channel 2 (see PLL and Frequency Synchronization). The
LTC3709 will be forced to operate in forced continuous
mode in this situation.
Fault Conditions: Current Limit
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3709, the maximum sense voltage is controlled by
the voltage on the V
RNG
pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
I
V
R
I
LIMIT
SNS MAX
DS ON T
L
=+
()
()
••
ρ
1
2
2
The current limit value should be checked to ensure that
I
LIMIT(MIN)
> I
OUT(MAX)
.
The minimum value of current limit
generally occurs with the largest V
IN
at the highest ambi-
ent temperature, conditions which cause the largest power
loss in the converter. Note that it is important to check for

LTC3709EUH#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Fast, 2-Phase Controller w/ Tracking
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