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PL123S-09SC-R

P1-P3P4-P6P7-P9
PL123S-05/-09
Spread-Compatible Low Skew Zero Delay Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1(408) 474- 1000 • www.micr el.com R ev 12/14/11 Page 1
FEATURES
Frequency Range 10MHz to 134 MHz
Output Options:
o 5 outputs PL123S-05
o 9 outputs PL123S-09
Zero input - output delay
Optional Drive Strength:
Standard (8mA) PL123S-05/-09
High (12mA) PL123S-05H/-09H
3.3V, ±10% operation
Available in Commercial and Industrial temperature
ranges
Available in 16-Pin SOP or TSSOP (PL123S-09),
and 8-Pin SOP (PL123S-05) packages
Spread-compatible with spread-spectrum modula-
tion clock inputs
DESCRIPTION
The PL123S-05/-09 (-05H/-09H for High Drive) are high
performance, low skew, low jitter zero delay buffers
designed to distribute high speed clocks. They have
one (PL123S-05) or two (PL123S-09) low-skew output
banks, of 4 outputs each, that are synchronized with
the input. The PL123S-09 allows control of the banks
of outputs by using the S1 and S2 inputs as shown in
the Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
PLL
REF CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
Mux
CLKB1
CLKB2
CLKB3
CLKB4
S1
S2
1REF
CLKA1
CLKA2
VDD
CLKOUT
CLKA4
CLKA3
VDD
PL123S-09
GND
CLKB4
CLKB3
S1
10
11
12
13
14
15
16
98
7
6
5
4
3
2
S2
CLKB2
CLKB1
GND
Bank B Bank A
Selector
Inputs
(PL123S-09 Only)
1
2
3
4
REF
5
6
7
8
CLKA2
CLKA1
GND
CLKOUT
CLKA4
VDD
CLKA3
PL123S-05
PL123S-05/-09
Spread-Compatible Low Skew Zero Delay Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1(408) 474- 1000 • www.micr el.com R ev 12/14/11 Page 2
PIN DESCRIPTIONS
Name
PL123S-09
PL123S-05
Type
Description
TSSOP-16L, SOP-16L
SOP-8L
REF
[1 ]
1
1
I
Input reference frequency
CLKA1
[2 ]
2
3
O
Buffered clock output, Bank A
CLKA2
[2 ]
3
2
O
Buffered clock output, Bank A
VDD
4,13
6
P
VDD connection
GND
5,12
4
P
GND connection
CLKB1
[2 ]
6
-
O
Buffered clock output, Bank B
CLKB2
[2 ]
7
-
O
Buffered clock output, Bank B
S2
[3 ]
8
-
I
Selector input
S1
[3 ]
9
-
I
Selector input
CLKB3
[2 ]
10
-
O
Buffered clock output, Bank B
CLKB4
[2 ]
11
-
O
Buffered clock output, Bank B
CLKA3
[2 ]
14
5
O
Buffered clock output, Bank A
CLKA4
[2 ]
15
7
O
Buffered clock output, Bank A
CLKOUT
[2 ]
16
8
O
Buffered clock output. Internal feedback
on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION FOR PL123S-09
S2
S1
CLOCK B1–B4
(Bank B)
CLKOUT
PLL Shutdown
0
0
Three-state
Driven
N
0
1
Three-state
Driven
N
1
0
Driven
Driven
Y
1
1
Driven
Driven
N
INPUT / OUTPUT SKEW CONTROL
The PL123S-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust-
ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact Micrel for more information.
PL123S-05/-09
Spread-Compatible Low Skew Zero Delay Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1(408) 474- 1000 • www.micr el.com R ev 12/14/11 Page 3
SPREAD COMPATIBLE
Many products today utilize spread-spectrum modulation clocking to reduce electromagnetic interference (EMI)
and pass FCC regulations. This product was designed to pass spread -spectrum input clock modulation frequen-
cies to the output. When a buffer is not designed to pass spread spectrum, there will exist significant tracking ji t-
ter between input and output clocks, which may result in problems with system timing and synchronization.
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bounc ing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20 
To CMOS Input
50 line
Connect a 33 series
resistor at each of the output
clocks to enhance the
stability of the output signal
P1-P3P4-P6P7-P9

PL123S-09SC-R

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Description:
Clock Buffer Low Skew 1:9 Zero Delay Buffe
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