LTC3828EUH#TRPBF Datasheet LTC3828EG#TRPBF, LTC3828EUH#TRPBF, LTC3828EUH#PBF | P10-P12

LTC3828

3828fc

OPERATION

(Refer to Functional Diagram)

Main Control Loop

The IC uses a constant frequency, current mode step-down

architecture with the two controller channels operating

180 degrees out of phase. During normal operation, each

top MOSFET is turned on when the clock for that channel

sets the RS latch, and turned off when the main current

comparator, I

, resets the RS latch. The peak inductor

current at which I

resets the RS latch is controlled by

the voltage on the I

pin, which is the output of each

error ampliﬁ er EA. The V

OSENSE

pin receives the voltage

feedback signal, which is compared to the internal refer-

ence voltage by the EA. When the load current increases,

it causes a slight decrease in V

OSENSE

relative to the 0.8V

reference, which in turn causes the I

voltage to increase

until the average inductor current matches the new load

current. After the top MOSFET has turned off, the bottom

MOSFET is turned on until either the inductor current

starts to reverse, as indicated by current comparator I

or the beginning of the next cycle.

The top MOSFET drivers are biased from ﬂ oating bootstrap

capacitor, C

, which normally is recharged during each off

cycle through an external diode when the top MOSFET

turns off. As V

decreases to a voltage close to V

OUT

the loop may enter dropout and attempt to turn on the

top MOSFET continuously. The dropout detector detects

this and forces the top MOSFET off for about 400ns every

tenth cycle to allow C

to recharge.

The main control loop is shut down by pulling the RUN

pin low. When the RUN pin reaches 1.5V, the main control

loop is enabled. When both RUN1 and RUN2 are low,

all controller functions are shut down, including the 5V

regulator.

Low Current Operation

The FCB/PLLIN pin is a multifunction pin providing two

functions: 1) to accept external clock signal; and 2) to

select among three modes of light load operations. When

the FCB/PLLIN pin voltage is below 0.75V, the control-

ler forces continuous PWM current mode operation. In

this mode, the top and bottom MOSFETs are alternately

turned on to maintain the output voltage independent of

direction of inductor current. When the FCB/PLLIN pin is

below V

INTVCC

– 0.7V but greater than 0.8V, the controller

enters Burst Mode operation. Burst Mode operation sets

a minimum output current level before inhibiting the top

switch and turns off the synchronous MOSFET(s) when

the inductor current goes negative. This combination of

requirements will, at low currents, force the I

pin below

a voltage threshold that will temporarily inhibit turn-on of

both output MOSFETs until the output voltage drops. There

is 60mV of hysteresis in the burst comparator B tied to

the I

pin. This hysteresis produces output signals to the

MOSFETs that turn them on for several cycles, followed by

a variable “sleep” interval depending upon the load current.

The resultant output voltage ripple is held to a very small

value by having the hysteretic comparator after the error

ampliﬁ er gain block. When the FCB/PLLIN pin voltage is

above 4.8V, the controller operates in constant frequency

mode and the synchronous MOSFET is turned off when

inductor current nears zero in each cycle.

In order to prevent erratic operation if no external con-

nections are made to the FCB/PLLIN pin, the FCB/PLLIN

pin has a 0.18µA internal current source pulling the pin

high.

The following table summarizes the possible states avail-

able on the FCB/PLLIN pin:

Table 1

FCB/PLLIN PIN CONDITION

0V to 0.75V Forced Continuous Both Controllers

(Current Reversal Allowed—

Burst Inhibited)

0.85V < V

FCB/PLLIN

< 4.3V

or Open

Minimum Peak Current Induces

Burst Mode Operation

No Current Reversal Allowed

>4.8V Burst Mode Operation Disabled

Constant Frequency Mode Enabled

No Current Reversal Allowed

No Minimum Peak Current

Besides providing a logic input to select light load op-

eration mode, the FCB/PLLIN pin acts as the input for

external clock synchronization. Upon detecting the pres-

ence of an external clock signal, channel 1 will lock on to

this external clock and this will be followed by channel 2

(see Frequency Synchronization section). The LTC3828

defaults to forced continuous mode when sychronized to

an external clock.

LTC3828

3828fc

OPERATION

(Refer to Functional Diagram)

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be

synchronized to an external source via the FCB/PLLIN pin.

The output of the phase detector at the PLLFLTR pin is

also the DC frequency control input of the oscillator that

operates over a 260kHz to 550kHz range corresponding

to a DC voltage input from 0V to 2.4V. When locked, the

PLL aligns the turn on of the top MOSFET to the rising

edge of the synchronizing signal.

The internal master oscillator runs at a frequency twelve

times that of each phase switching frequency. The PHSMD

pin (UH package only) determines the relative phases

between the internal controllers as well as the CLKOUT

signal as shown in Table 2. The phases tabulated are rela-

tive to zero phase being deﬁ ned as the rising edge of the

top gate (TG1) driver output of controller 1.

Table 2

PHSMD

GND OPEN INTV

Controller 1 0° 0° 0°

Controller 2 180° 180° 240°

CLKOUT 60° 90° 120°

The CLKOUT signal can be used to synchronize additional

power stages in a multiphase power supply solution feeding

a single, high current output or separate outputs. Input

capacitance ESR requirements and efﬁ ciency losses are

substantially reduced because the peak current drawn from

the input capacitor is effectively divided by the number of

phases used and power loss is proportional to the RMS

current squared. A 2-phase, single output voltage imple-

mentation can reduce input path power loss by 75% and

radically reduce the required RMS current rating of the

input capacitor(s).

In the G28 package, CLKOUT is 90° out of phase with

channel 1 and channel 2.

Constant Frequency Operation

When the FCB/PLLIN pin is tied to INTV

, Burst Mode

operation is disabled and the forced minimum output

current requirement is removed. This provides constant

frequency, discontinuous current (preventing reverse

inductor current) operation over the widest possible output

current range. This constant frequency operation is not

as efﬁ cient as Burst Mode operation, but does provide a

lower noise, constant frequency operating mode down

to approximately 1% of the designed maximum output

current.

Continuous Current (PWM) Operation

Tying the FCB/PLLIN pin to ground will force continuous

current operation. This is the least efﬁ cient operating mode,

but may be desirable in certain applications. The output

can source or sink current in this mode. When sinking

current while in forced continuous operation, current will

be forced back into the main power supply potentially

boosting the input supply level.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>7.5%) as well as other more serious condi-

tions that may overvoltage the output. In this case, the top

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

Power Good (PGOOD) Pin

The PGOOD pin is connected to an open drain of an internal

MOSFET. The MOSFET turns on and pulls the pin down

when the enabled channel’s output is not within ±7.5% of

the nominal output level as determined by the feedback

resistor divider. When the enabled channel’s output meets

the ±7.5% requirement, the MOSFET is turned off within

10µs and the pin is allowed to be pulled up by an external

resistor to source of up to 5.5V. If either channel 1 or chan-

nel 2 is shut down by driving its RUN pin low, PGOOD will

ignore the state of that channel’s ouput.

Foldback Current

Foldback current limiting is activated when the output

voltage falls below 70% of its nominal level. If a short

is present, a safe, low output current is provided due to

internal current foldback and actual power wasted is low

due to the efﬁ cient nature of the current mode switching

regulator. This function is disabled at start-up.

LTC3828

3828fc

OPERATION

(Refer to Functional Diagram)

THEORY AND BENEFITS OF 2-PHASE OPERATION

The LTC3728 and the LTC3828 family of dual high efﬁ -

ciency DC/DC controllers brings the considerable beneﬁ ts

of 2-phase operation to portable applications for the ﬁ rst

time. Notebook computers, PDAs, handheld terminals and

automotive electronics will all beneﬁ t from the lower input

ﬁ ltering requirement, reduced electromagnetic interference

(EMI) and increased efﬁ ciency associated with 2-phase

operation.

Why the need for 2-phase operation? Up until the 2-phase

family, constant-frequency dual switching regulators

operated both channels in phase (i.e., single-phase

operation). This means that both switches turned on at

the same time, causing current pulses of up to twice the

amplitude of those for one regulator to be drawn from the

input capacitor and battery. These large amplitude current

pulses increased the total RMS current ﬂ owing from the

input capacitor, requiring the use of more expensive input

capacitors and increasing both EMI and losses in the input

capacitor and battery.

With 2-phase operation, the two channels of the dual-

switching regulator are operated 180 degrees out of phase.

This effectively interleaves the current pulses drawn by the

switches, greatly reducing the overlap time where they add

together. The result is a signiﬁ cant reduction in total RMS

input current, which in turn allows less expensive input

capacitors to be used, reduces shielding requirements for

EMI and improves real world operating efﬁ ciency.

Figure 2 compares the input waveforms for a representa-

tive single-phase dual switching regulator to the LTC3828

2-phase dual switching regulator. An actual measurement of

the RMS input current under these conditions shows that

2-phase operation dropped the input current from 2.6A

RMS

to 1.9A

RMS

. While this is an impressive reduction in itself,

remember that the power losses are proportional to I

RMS

meaning that the actual power wasted is reduced by a fac-

tor of 1.86. The reduced input ripple voltage also means

less power is lost in the input power path, which could

include batteries, switches, trace/connector resistances

and protection circuitry. Improvements in both conducted

and radiated EMI also directly accrue as a result of the

reduced RMS input current and voltage.

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

voltage V

(Duty Cycle = V

OUT

). Figure 3 shows how

the RMS input current varies for single-phase and 2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

It can readily be seen that the advantages of 2-phase opera-

tion are not just limited to a narrow operating range, but

in fact extend over a wide region. A good rule of thumb

for most applications is that 2-phase operation will reduce

the input capacitor requirement to that for just one channel

operating at maximum current and 50% duty cycle.

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

100mA/DIV

N(MEAS)

= 2.6A

RMS

N(MEAS)

= 1.9A

RMS

(a) (b)

Figure 2. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators

Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC3828 2-Phase Regulator Allows

Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efﬁ ciency

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

LTC3828EUH#TRPBF

Mfr. #:

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Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators Dual, 2-Phase Controller, w/ Tracking PLL

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LTC3828EUH#TRPBF

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