LTC3828
25
3828fc
APPLICATIONS INFORMATION
P
V
V
CC
V
A
pF
kHz mW
MAIN
=
()
+°°
[]
Ω
()
+
()
⎛
⎝
⎜
⎞
⎠
⎟
Ω
()( )
+
⎡
⎣
⎢
⎤
⎦
⎥
()
=
18
22
5 1 0 005 50 25
0 035 22
5
2
4 215
1
523
1
23
300 332
2
2
.
( . )( – ) •
.•
–. .
A short-circuit to ground will result in a folded back cur-
rent of:
I
mV ns V
H
A
SC
=
Ωμ
⎛
⎝
⎜
⎞
⎠
⎟
=
25
001
1
2
120 22
33
21
.
–
()
.
.
with a typical value of R
DS(ON)
and δ = (0.005/°C)(20) =
0.1. The resulting power dissipated in the bottom MOSFET
is:
P
VV
V
A
mW
SYNC
=
()( )
Ω
()
=
22 1 8
22
2 1 1 125 0 022
100
2
–.
...
which is less than under full-load conditions.
C
IN
is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. C
OUT
is
chosen with an ESR of 0.02 for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V
ORIPPLE
= R
ESR
(ΔI
L
) = 0.02(1.67A) = 33mV
P-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 12. The Figure 13 illustrates the
current waveforms present in the various branches of the
2-phase synchronous regulators operating in the continu-
ous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at CIN? Do not attempt to split the input decoupling for
the two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C
INTVCC
must return to the combined C
OUT
(–) terminals.
The path formed by the top N-channel MOSFET, Schottky
diode and the C
IN
capacitor should have short leads and
PC trace lengths. The output capacitor (–) terminals should
be connected as close as possible to the (–) terminals
of the input capacitor by placing the capacitors next to
each other and away from the Schottky loop described
above.
3. Do the LTC3828 V
OSENSE
pins’ resistive dividers connect
to the (+) terminals of C
OUT
? The resistive divider must
be connected between the (+) terminal of C
OUT
and signal
ground. The R2 and R4 connections should not be along
the high current input feeds from the input capacitor(s).
4. Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing? The fi lter capacitor between
SENSE
+
and SENSE
–
should be as close as possible to
the IC. Ensure accurate current sensing with Kelvin con-
nections at the SENSE resistor.
5. Is the INTV
CC
decoupling capacitor connected close to
the IC, between the INTV
CC
and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTV
CC
and PGND pins can help improve noise
performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC3828 and occupy minimum PC trace area.
7. Use a modifi ed “star ground” technique: a low imped-
ance, large copper area central grounding point on the same
side of the PC board as the input and output capacitors with
tie-ins for the bottom of the INTV
CC
decoupling capacitor,
the bottom of the voltage feedback resistive divider and
the SGND pin of the IC.
