Data Sheet ADuM110N
Rev. 0 | Page 5 of 16
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity
2
|CM
H
| 75 100 kV/µs
V
I
= V
DD1
, V
CM
= 1000 V, transient
magnitude = 800 V
|CM
L
| 75 100 kV/µs
V
I
= 0 V, V
CM
= 1000 V, transient
magnitude = 800 V
1
N0 indicates the ADuM110N0 models and N1 indicates the ADuM110N1 models. See the Ordering Guide section.
2
|CM
H
| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V
O
) > 0.8 V
DD2
. |CM
L
| is the maximum common-
mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 4. Total Supply Current vs. Data Throughput—3.3 V Operation
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
Supply Current Side 1 I
DD1
2.2 3.5 2.4 3.6 3.2 4.6 mA
Supply Current Side 2 I
DD2
0.9 1.5 1.4 2.0 2.8 4.3 mA
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ V
DD1
≤ 2.75 V, 2.25 V ≤ V
DD2
≤ 2.75 V, −40°C ≤ T
A
≤ +125°C, unless otherwise noted. Switching specifications
are tested with C
L
= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate 150 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
5.0 7.0 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |t
PLH
− t
PHL
|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew t
PSK
7.0 ns
Between any two units at the
same temperature, voltage, load
Jitter 320 ps p-p See the Jitter Measurement section
65 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold
Logic High V
IH
0.7 × V
DD1
V
Logic Low V
IL
0.3 × V
DD1
V
Output Voltage
Logic High V
OH
V
DD2
− 0.1 V
DD2
V I
O
= −20 µA, V
I
= V
IH
V
DD2
− 0.4 V
DD2
− 0.2 V I
O
= −2 mA, V
I
= V
IH
Logic Low V
OL
0.0 0.1 V I
O
= 20 µA, V
I
= V
IL
0.2 0.4 V I
O
= 2 mA, V
I
= V
IL
Input Current per Channel I
I
−10 +0.01 +10 µA 0 V ≤ V
I
≤ V
DD1
Quiescent Supply Current
I
DD1 (Q)
0.8 1.1 mA V
I
= 0 (N0), 1 (N1)
1
I
DD2 (Q)
0.9 1.2 mA V
I
= 0 (N0), 1 (N1)
1
I
DD1 (Q)
3.5 5.6 mA V
I
= 1 (N0), 0 (N1)
1
I
DD2 (Q)
1.0 1.2 mA V
I
= 1 (N0), 0 (N1)
1
Dynamic Supply Current
Dynamic Input I
DDI (D)
0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output I
DDO (D)
0.01 mA/Mbps Inputs switching, 50% duty cycle
