REV. 0
ADE7751
–10–
THEORY OF OPERATION
The two ADCs digitize the voltage and current signals from the
current and voltage transducers. These ADCs are 16-bit second
order sigma-delta converters with an oversampling rate of 900 kHz.
This analog input structure greatly simplifies transducer interfacing
by providing a wide dynamic range for direct connection to the
transducer and also by simplifying the antialiasing filter design.
A programmable gain stage in the current channel further
facilitates easy transducer interfacing. A high-pass filter in the
current channel removes any dc component from the current
signal. This eliminates any inaccuracies in the real power calcu-
lation due to offsets in the voltage or current signals—see
HPF and Offset Effects section.
The real power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals. In order
to extract the real power component (i.e., the dc component), the
instantaneous power signal is low-pass filtered. Figure 2 illustrates
the instantaneous real power signal and shows how the real power
information can be extracted by low-pass filtering the instantaneous
power signal. This scheme correctly calculates real power for
nonsinusoidal current and voltage waveforms at all power factors.
All signal processing is carried out in the digital domain for
superior stability over temperature and time.
LPF
DIGITAL-TO-
FREQUENCY
F1
F2
CH1
MULTIPLIER
PGA
CH2
ADC
VI
2
VI
VI
2
p(t) = i(t)v(t)
WHERE:
v(t) = Vcos(t)
i(t) = Icos(t)
p(t) =
VI
2
{
1+cos(2t)}
ADC
TIME
HPF
DIGITAL-TO-
FREQUENCY
CF
INSTANTANEOUS REAL
POWER SIGNAL
INSTANTANEOUS
POWER SIGNAL – p(t)
Figure 2. Signal Processing Block Diagram
The low-frequency output of the ADE7751 is generated by
accumulating this real power information. This low frequency
inherently means a long accumulation time between output
pulses. The output frequency is therefore proportional to the
average real power. This average real power information can in
turn be accumulated (e.g., by a counter) to generate real-energy
information. Because of its high output frequency, and hence
shorter integration time, the CF output is proportional to the
instantaneous real power. This is useful for system calibration
purposes that would take place under steady load conditions.
Power Factor Considerations
The method used to extract the real power information from the
instantaneous power signal (i.e., by low-pass filtering) is still
valid even when the voltage and current signals are not in phase.
Figure 3 displays the unity power factor condition and a DPF
(displacement power factor) = 0.5, i.e., current signal lagging
the voltage by 60°. If we assume the voltage and current waveforms
are sinusoidal, the real power component of the instantaneous
power signal (i.e., the dc term) is given by:
VI×
×°
()
2
60cos
(1)
This is the correct real power calculation.
INSTANTANEOUS
REAL POWER SIGNAL
INSTANTANEOUS
POWER SIGNAL
VI
2
cos(60)
VI
2
INSTANTANEOUS
POWER SIGNAL
INSTANTANEOUS
REAL POWER SIGNAL
60
CURRENT
VOLTAGE
CURRENT
VOLTAGE
0V
0V
Figure 3. DC Component of Instantaneous Power Signal
Conveys Real Power Information PF < 1
Nonsinusoidal Voltage and Current
The real power calculation method also holds true for nonsinu-
soidal current and voltage waveforms. All voltage and current
waveforms in practical applications will have some harmonic
content. Using the Fourier Transform, instantaneous voltage
and current waveforms can be expressed in terms of their
harmonic content.
vt V V h t
Oh h
h
() sin( )=+×
×+
2
0
ωα
(2)
where:
v(t)= The instantaneous voltage
V
O
= The average value
V
h
= The rms value of voltage harmonic h
and
h
= The phase angle of the voltage harmonic
it I I
h
ht
Oh h
() sin( )=+×
×+
2
0
ωβ
(3)
where:
i(t)=The instantaneous current
I
O
= The dc component
I
h
= The rms value of current harmonic h
and
h
=The phase angle of the current harmonic
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ADE7751
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Using Equations 2 and 3, the real power P can be expressed in
terms of its fundamental real power (P
1
) and harmonic real
power (P
H
).
P = P
1
+ P
H
where:
PVI
111 1
1
1
1
=
cos( )
φ
φαβ
(4)
and (5)
As shown in Equation 5 above, a harmonic real power compo-
nent is generated for every harmonic, provided that harmonic is
present in both the voltage and current waveforms. The power
factor calculation has been shown previously to be accurate in
the case of a pure sinusoid, therefore the harmonic real power
must also correctly account for the power factor since it is made
up of a series of pure sinusoids.
Note that the input bandwidth of the analog inputs is 14 kHz
with a master clock frequency of 3.5795 MHz.
ANALOG INPUTS
Channel V2 (Voltage Channel)
The output of the line voltage transducer is connected to the
ADE7751 at this analog input. Channel V2 is a fully differen-
tial voltage input. The maximum peak differential signal on
Channel 2 is ±660 mV. Figure 4 illustrates the maximum
signal levels that can be connected to the ADE7751 Channel 2.
DIFFERENTIAL INPUT
600mV MAX PEAK
+600mV
AGND
V
CM
V2
V2P
V
CM
–600mV
COMMON MODE
100mV MAX
V2N
V2
Figure 4. Maximum Signal Levels, Channel 2
Channel 2 must be driven from a common-mode voltage, i.e.,
the differential voltage signal on the input must be referenced to
a common mode (usually AGND). The analog inputs of the
ADE7751 can be driven with common-mode voltages of up to
100 mV with respect to AGND. However, best results are
achieved using a common mode equal to AGND.
Channel V1 (Current Channel)
The voltage outputs from the current transducers are connected
to the ADE7751 here. Channel V1 has two voltage inputs, namely
V1A and V1B. These inputs are fully differential with respect to
V1N. However, at any one time, only one is selected to perform
the power calculation—see Fault Detection section.
The analog inputs V1A, V1B, and V1N have the same maximum
signal level restrictions as V2P and V2N. However, Channel 1
has a programmable gain amplifier (PGA) with user-selectable
gains of 1, 2, 8, or 16—see Table I. These gains facilitate easy
transducer interfacing.
Figure 5 illustrates the maximum signal levels on V1A, V1B,
and V1N. The maximum differential voltage is ±660 mV divided
by the gain selection. Again, the differential voltage signal on the
inputs must be referenced to a common mode, e.g., AGND. The
maximum common-mode signal is ±100 mV as shown in Figure 5.
V1A, V1B
DIFFERENTIAL INPUT A
660mV/GAIN MAX PEAK
AGND
V
CM
V1A
V
CM
–660mV
GAIN
COMMON MODE
100mV MAX
V1N
+660mV
GAIN
V1
V1B
DIFFERENTIAL INPUT B
660mV/GAIN MAX PEAK
V1
Figure 5. Maximum Signal Levels, Channel 1
Table I.
Maximum
G1 G0 Gain Differential Signal
00 1±660 mV
01 2±330 mV
10 8±82 mV
11 16±41 mV
Typical Connection Diagrams
Figure 6 shows a typical connection diagram for Channel V1.
Here the analog inputs are being used to monitor both the
phase and neutral currents. Because of the large potential
difference between the phase and neutral, two CTs (current
transformers) must be used to provide the isolation. Notice
both CTs are referenced to AGND (analog ground), hence
the common-mode voltage is 0 V. The CT turns ratio and
burden resistor (Rb) are selected to give a peak differential
voltage of ±660 mV/gain.
V1B
660mV
GAIN
CT
IN
V1A
AGND
Rb
R
f
CT
NEUTRALPHASE
IP
V1N
C
f
C
f
Rb
660mV
GAIN
R
f
Figure 6. Typical Connection for Channel 1
PVI
Hhh h
hhh
h
=
××
=
1
cos( )
φ
φαβ
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ADE7751
–12–
Figure 7 shows two typical connections for Channel V2. The first
option uses a PT (potential transformer) to provide complete isola-
tion from the mains voltage. In the second option, the ADE7751
is biased around the neutral wire and a resistor divider is used to
provide a voltage signal that is proportional to the line voltage.
Adjusting the ratio of Ra and Rb is also a convenient way of
carrying out a gain calibration on the meter.
660mV
Ra
Rb
VR
V2P
AGND
R
f
R
f
CT
NEUTRALPHASE
V2N
C
f
C
f
660mV
V2P
R
f
NEUTRALPHASE
V2N
C
f
C
f
NOTE
Ra
R
f
;
Rb + VR = R
f
Figure 7. Typical Connections for Channel 2
POWER SUPPLY MONITOR
The ADE7751 contains an on-chip power supply monitor. The
analog supply (AV
DD
) is continuously monitored by the ADE7751.
If the supply is less than 4 V ± 5%, the ADE7751 will be reset.
This is useful to ensure correct device start up at power-up and
power-down. The power supply monitor has built-in hysteresis
and filtering. This gives a high degree of immunity to false
triggering due to noisy supplies.
As can be seen in Figure 8, the trigger level is nominally set at 4 V.
The tolerance on this trigger level is about ±5%. The power supply
and decoupling for the part should be such that the ripple at AV
DD
does not exceed 5 V ± 5% as specified for normal operation.
AV
DD
5V
4V
0V
INTERNAL
RESET
RESET
TIME
ACTIVE RESET
Figure 8. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 9 shows the effect of offsets on the real power calculation. As
shown in Figure 9, an offset on Channel 1 and Channel 2 will
contribute a dc component after multiplication. Since this dc
component is extracted by the LPF and used to generate the real
power information, the offsets will have contributed a constant
error to the real power calculation. This problem is easily avoided by
enabling the HPF (i.e., pin AC/DC is set logic high) in Channel 1.
By removing the offset from at least one channel, no error component
can be generated at dc by the multiplication. Error terms at cos(ωt)
are removed by the LPF and the digital-to-frequency conversion—
see Digital-to-Frequency Conversion section.
VtV I tI
VI
VIVI t
VI t
VI
t
OS OS
OS OS OS
OS
cos( ) cos( )
cos( )
cos( ) cos( )
ωω
ω
ωω
+
()
×× +
()
=
×
×
× +
×
×
2
2
2
V
OS
I
OS
I
OS
V
V
OS
I
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
2
FREQUENCY – RAD/S
2
V I
0
Figure 9. Effect of Channel Offsets on the
Real Power Calculation
The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figures 10 and 11 show the phase error between chan-
nels with the compensation network activated. The ADE7751
is phase compensated up to 1 kHz as shown. This will ensure
correct active harmonic power calculation even at low-power factors.
FREQUENCY – Hz
0
100
PHASE – Degrees
–0.05
–0.10
0
0.05
0.10
0.15
0.20
0.25
0.30
200 300 400 500 600 700 800 900 1000
Figure 10. Phase Error Between Channels (0 Hz to 1 kHz)

ADE7751ARSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized SGL Phase Energy Metering IC
Lifecycle:
New from this manufacturer.
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