REV. 0
–13–
ADE7751
FREQUENCY – Hz
40
PHASE – Degrees
–0.05
–0.10
0
0.05
0.10
0.15
0.20
0.25
0.30
45 50 55 60 65 70
Figure 11. Phase Error Between Channels (40 Hz to 70 Hz)
DIGITAL-TO-FREQUENCY CONVERSION
As previously described, the digital output of the low-pass filter
after multiplication contains the real power information. However,
since this LPF is not an ideal “brick wall” filter implementation,
the output signal also contains attenuated components at
the line frequency and its harmonics, i.e., cos(hωt) where
h = 1, 2, 3, . . . and so on.
The magnitude response of the filter is given by:
Hf
fHz
()
=
+
()
1
189/.
(6)
For a line frequency of 50 Hz, this would give an attenuation of
the 2 ω (100 Hz) component of approximately –22 dB. The
dominating harmonic will be at twice the line frequency, i.e.,
cos(2ωt), due to the instantaneous power signal.
Figure 12 shows the instantaneous real power signal output of LPF,
which still contains a significant amount of instantaneous power
information, i.e., cos(2ωt). This signal is then passed to the
digital-to-frequency converter where it is integrated (accumulated)
over time in order to produce an output frequency. This
accumulation of the signal will suppress or average out any
non-dc components in the instantaneous real power signal. The
average value of a sinusoidal signal is zero. Hence, the frequency
generated by the ADE7751 is proportional to the average real
power. Figure 12 shows the digital-to-frequency conversion
for steady load conditions, i.e., constant voltage and current.
As shown in the diagram, the frequency output CF varies over
time, even under steady load conditions. This frequency variation
is primarily due to the cos(2ωt) component in the instantaneous
real power signal. The output frequency on CF can be up to 128
times higher than the frequency on F1 and F2. This higher
output frequency is generated by accumulating the instantaneous
real power signal over a much shorter time while converting it to
a frequency. This shorter accumulation period means less aver-
aging of the cos(2ωt) component. As a consequence, some of
this instantaneous power signal passes through the digital-to-
frequency conversion. This will not be a problem in the application.
Where CF is used for calibration purposes, the frequency should
be averaged by the frequency counter. This will remove any ripple.
If CF is being used to measure energy, e.g., in a microprocessor-
based application, the CF output should also be averaged to
calculate power. However, if an energy measurement is being
made by counting pulses, no averaging is required. Because the
outputs F1 and F2 operate at a much lower frequency, a lot
more averaging of the instantaneous real power signal is carried
out. The result is a greatly attenuated sinusoidal content and a
virtually ripple-free frequency output.
2
V ⴛ I
2
FREQUENCY – RAD/S
LPF
DIGITAL-TO-
FREQUENCY
F1
F2
⌺
⌺
DIGITAL-TO-
FREQUENCY
CF
INSTANTANEOUS REAL POWER SIGNAL
(FREQUENCY DOMAIN)
MULTIPLIER
TIME
FREQUENCY
F1
FREQUENCY
CF
TIME
V
I
0
LPF TO EXTRACT
REAL POWER
(DC TERM)
cos(2t)
ATTENUATED BY LPF
Figure 12. Real Power-to-Frequency Conversion
FAULT DETECTION
The ADE7751 incorporates a novel fault detection scheme that
warns of fault conditions and allows the ADE7751 to continue
accurate billing during a fault event. The fault detection function is
designed to work over a line frequency of 45 Hz to 55 Hz. The
ADE7751 does this by continuously monitoring both the phase
and neutral (return) currents. A fault is indicated when these
currents differ by more than 12.5%. However, even during a
fault, the output pulse rate on F1 and F2 is generated using the
larger of the two currents. Because the ADE7751 looks for a
difference between the signals on V1A and V1B, it is important
that both current transducers are closely matched.
On power-up the output pulse rate of the ADE7751 is proportional
to the product of the signals on Channel V1A and Channel 2. If
there is a difference of greater than 12.5% between V1A and
V1B on power-up, the fault indicator (FAULT) will go active
after about one second. In addition, if V1B is greater than V1A
the ADE7751 will select V1B as the input. The fault detection is
automatically disabled when the voltage signal on Channel 1 is less
than 0.5% of the full-scale input range. This will eliminate false
detection of a fault due to noise at light loads.
Fault with Active Input Greater than Inactive Input
If V1A is the active current input (i.e., is being used for billing),
and the signal on V1B (inactive input) falls by more than 12.5%
of V1A, the fault indicator will go active. Both analog inputs are
filtered and averaged to prevent false triggering of this logic
output. As a consequence of the filtering, there is a time delay of
approximately one second on the logic output FAULT after the
fault event. The FAULT logic output is independent of any activ-
ity on outputs F1 or F2. Figure 13 illustrates one condition under
which FAULT becomes active. Since V1A is the active input and it
is still greater than V1B, billing is maintained on VIA, i.e., no swap
to the V1B input will occur. V1A remains the active input.
