L98SI013TR Datasheet L98SI, L98SI013TR | P4-P6

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ELECTRICAL CHARACTERISTICS

(Continued)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

INPUT BUFFER (SI, CE, SCLK and RESET pins)

T–

Threshold Voltage at

Falling Edge

SCLK only

= 5V

10% 0.2V

0.6

T+

Threshold Voltage at

Rising Edge

SCLK only

= 5V

10% 0.7V

4.15

Hysteresis Voltage V

T+

– V

T–

0.85 2.5 V

Input Current V

= 5.50V, 0 < V

< V

– 10 + 10

Input Capacitance 0 < V

< V

20 nF

OUTPUT BUFFER (SO pin)

SOL

Output LOW Voltage I

= 1.6mA 0.4 V

SOH

Output HIGH Voltage I

= 0.8mA V

– 1.3V

SOtl

Output Tristate Leakage

Current

0 < V

< V

, CE Pin Held High,

= 5.25V

– 20 20

Output Capacitance 0 < V

< V

CE Pin Held High

20 pF

Quiescent Supply

Current at V

All Outputs Progr. ON. I

= 0.5A

per Output Simultaneously

10 mA

SERIAL PERIPHERAL INTERFACE (see fig. 2, timing diagram)

Operating Frequency D.C. 2 MHz

lead

Enable Lead Time 250 ns

lag

Enable Lag Time 250 ns

wSCKH

Clock HIGH Time 200 ns

wSCKL

Clock LOW Time 200 ns

Data Setup Time 75 ns

Data Hold Time 75 ns

Enable Time 250 ns

DIS

Disable Time 250 ns

Data Valid Time 100 ns

rSO

Rise Time (SO output) V

= 20 to 70% C

= 200pF 50 ns

fSO

Fall Time (SO output) V

= 70 to 20% C

= 200pF 50 ns

rSI

Rise Time SPI

Inputs (SCK, SI, CE)

= 20 to 70% C

= 200pF 200 ns

fSI

Fall Time SPI

Inputs (SCLK, SI, CE)

= 70 to 20% C

= 200pF 200 ns

Output Data Hold Time 0

L98SI

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The L98SI DMOS output is a low operating power de-

vice featu-ring, eight 1Ω R

DSON

DMOS drivers with

transient protection circuits in output stages. Each

channel is independently controlled by an output

latch and a common RESET line which disables all

eight outputs. The driver has low saturation and short

circuit protection and can drive inductive and resistive

loads such as solenoids, lamps and relais. Data is

transmitted to the device serially using the Serial Pe-

ripheral Interface (SPI) protocol. The circuit receives

8 bit serial data by means of the serial input (SI) which

is stored in an internal register to control the output

drivers. The serial output (SO) provides 8 bit of diag-

nostic data representing the voltage level at the driver

output. This allows the microprocessor to diagnose

the condition of the output drivers.

The output saturation voltage is monitored by a

comparator for an out of saturation condition and is

able to unlatch the particular driver through the fault

reset line. This circuit is also cascadable with an-

other octal driver in order to jam 8 bit multiple data.

The device is selected when the chip enable (CE)

line is low.

Additionally the (SO) is placed in a tri-state mode

when the device is deselected. The negative edge

of the (CE) transfers the voltage level of the drivers

to the shift register and the positive edge of the (CE)

latches the new data from the shift register to the

drivers. When CE is Low, data bit contained into the

shift register is transferred to SO output at every

SCLK positive transition while data bit present at SI

input is latched into the shift register on every SCLK

negative transition.

Internal Blocks Description

The internal architecture of the device is based on

the three internal major blocks : the octal shift reg-

ister for talking to the SPI bus, the octal latch for hold-

ing control bits written into the device and the octal

load driver array.

Shift Register

The shift register has both serial and parallel inputs

and serial and parallel outputs. The serial input ac-

cepts data from the SPI bus and the serial output

simultaneously sends data into the SPI bus. The

parallel outputs are latched into the parallel latch in-

side the L98SI at the end of a data transfer. The par-

allel inputs jam diagnostic data into the shift register

at the beginning of a data transfer cycle.

Parallel Latch

The parallel latch holds the input data from the shift

Individual registers in the latch may be cleared by

fault conditions in order to protect the overloaded

output stages. The entire latch may also be cleared

by the RESET signal.

Output Stages

The output stages provide an active low drive signal

suitable for 0.75A continuous loads. Each output

has a current limit circuit which limits the maximum

output current to at least 1.05A to allow for high in-

rush currents. Additionally, the outputs have internal

zeners set to 36 volts to clamp inductive transients

at turn-off. Each output also has a voltage compara-

tor observing the output node. If the voltage exceeds

1.8V on an ON output pin, a fault condition is as-

sumed and the latch driving this particular stage is

reset, turning the output OFF to protect it. The timing

of this action is described below. These compara-

tors also provide diagnostic feedback data to the

shift register. Additionally, the comparators contain

an internal pulldown current which will cause the cell

to indicate a low output voltage if the output is pro-

grammed OFF and the output pin is open circuited.

TIMING DATA TRANSFER

Figure #2 shows the overall timing diagram from a

byte transfer to and from the L98SI using the SPI

bus.

CE High to Low Transition

The action begins when the Chip Enable (CE) pin is

pulled low. The tri-state Serial Output (SO) pin driver

will be enabled entire time that CE is low. At the fall-

ing edge of the CE pin, the diagnostic data from the

voltage comparators in the output stages will be

latched into the shift register. If a particular output is

high, a logic one will be jammed into that bit in the

shift register. If the output is low, a logic zero will be

loaded there. The most significant bit (07) should be

presented at the Serial Input (SI) pin. A zero at this

pin will program an output ON, while a one will pro-

gram the output OFF.

SCLK

Transitions

The Serial Clock (SCLK) pin should then be pulled

high. At this point the diagnostic bit from the most

significant output (07) will appear at the SO pin. A

high here indicates that the 07 pin is higher than

1.8V. The SCLK pin should then be toggled low then

high. New SO data will appear following every rising

edge of SCLK and new SI data will be latched into

the L98SI shift register on the falling edges. An un-

limited amount of data may be shifted through the

device shift register (into the SI pin and out the SO

FUNCTIONAL DESCRIPTION

L98SI

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pin), allowing the other SPI devices to be cascaded

in a daisy chain with the L98SI.

CE Low to High Transition

Once the last data bit has been shifted into the

L98SI, the CE pin should be pulled high.

At the rising edge of CE the shift register data is

latched into the parallel latch and the output stages

will be actuated by the new data. An internal 160µs

delay timer will also be started at this rising edge

(see t

). During the 160µs period, the outputs will

be protected only by the analog current limiting cir-

cuits since the resetting of the parallel latches by

faults conditions will be inhibited during this period.

This allows the part to overcome any high inrush cur-

rents that may flow immediately after turn on. Once

the delay period has elapsed, the output voltages

are sensed by the comparators and any output with

voltages higher than 1.8V are latched OFF. It should

be noted that the SCLK pin should be low at both

transitions of the CE pin to avoid any false clocking

of the shift register. The SCLK input is gated by the

CE pin, so that the SCLK pin is ignored whenever

the CE pin is high.

FAULT CONDITIONS CHECK

Checking for fault conditions may be done in the fol-

lowing way. Clock in a new control byte. Wait 160

microseconds or so to allow the outputs to settle.

Clock in the same control byte and observe the diag-

nostic data that comes out of the device. The diag-

nostic bits should be identical to the bits that were

first clocked in. Any differences would point to a fault

on that output. If the output was programmed ON by

clocking in a zero, and a one came back as the di-

agnostic bit for that output, the output pin was still

high and a short circuit or overload condition exists.

If the output was programmed OFF by clocking in a

one, and a zero came back as the diagnostic bit for

that output, nothing had pulled the output pin high

and it must be floating, so an open circuit condition

exists for that output.

Figure 1

: Byte Timing with Asynchronous Reset.

L98SI

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L98SI013TR

Mfr. #:

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Description:

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L98SI013TR

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