LTC4215/LTC4215-2
16
4215fe
APPLICATIONS INFORMATION
and C2 are cleared by removal of the fault condition, the
switch is allowed to turn on again.
The LTC4215 will set bit D2 and turn off in the event of
an overcurrent fault, preventing it from remaining in an
overcurrent condition. If confi gured to auto-retry, the
LTC4215 will continually attempt to restart after cool-down
cycles until it succeeds in starting up without generating
an overcurrent fault.
Data Converter
The LTC4215 incorporates an 8-bit ∆∑ A/D converter
that continuously monitors three different voltages. The
∆∑ architecture inherently averages signal noise during
the measurement period. The SOURCE pin has a 1/12.5
resistive divider to monitor a full scale voltage of 15.4V
with 60mV resolution. The ADIN pin is monitored with a
1.235V full scale and 4.82mV resolution, and the voltage
between the V
DD
and SENSE pins is monitored with a
38.6mV full scale and 151µV resolution.
Results from each conversion are stored in registers E
(Sense), F (Source) and G (ADIN), as seen in Tables 6-8,
and are updated 10 times per second. Setting CONTROL
register bit A5 invokes a test mode that halts the data
converter so that registers E, F, and G may be written to
and read from for software testing.
Confi guring the GPIO Pin
Table 2 describes the possible states of the GPIO pin using
the control register bits A6 and A7. At power-up, the default
state is for the GPIO pin to go high impedance when power
is good (FB pin greater than 1.235V). Other applications
for the GPIO pin are to pull down when power is good, a
general purpose output and a general purpose input.
Current Limit Stability
For many applications the LTC4215 current limit will be
stable without additional components. However there are
certain conditions where additional components may be
needed to improve stability. The dominant pole of the cur-
rent limit circuit is set by the capacitance and resistance at
the gate of the external MOSFET, and larger gate capaci-
tance makes the current limit loop more stable. Usually
a total of 8nF gate to source capacitance is suffi cient for
stability and is typically provided by inherent MOSFET C
GS
,
however the stability of the loop is degraded by increasing
R
SENSE
or by reducing the size of the resistor on a gate RC
network if one is used, which may require additional gate
to source capacitance. Board level short-circuit testing
in highly recommended as board layout can also affect
transient performance, for stability testing the worst case
condition for current limit stability occurs when the output
is shorted to ground after a normal startup.
There are two possible parasitic oscillations when the
MOSFET operates as a source follower when ramping
at power-up or during current limiting. The fi rst type of
oscillation occurs at high frequencies, typically above
1MHz. This high frequency oscillation is easily damped
with R5 as shown in Figure 1. In some applications, one
may fi nd that R5 helps in short-circuit transient recovery
as well. However, too large of an R5 value will slow down
the turn-off time. The recommended R5 range is between
5 and 500.
The second type of source follower oscillation occurs at
frequencies between 200kHz and 800kHz due to the load
capacitance being between 0.2µF and 9µF, the presence
of R5 resistance, the absence of a drain bypass capacitor,
a combination of bus wiring inductance and bus supply
output impedance. To prevent this second type of oscillation
avoid load capacitance below 10µF, alternately connect an
external capacitor from the MOSFET gate to ground with
a value greater than 1.5µF.
Supply Transients
The LTC4215 is designed to ride through supply transients
caused by load steps. If there is a shorted load and the
parasitic inductance back to the supply is greater than
0.5µH, there is a chance that the supply collapses before
the active current limit circuit brings down the GATE pin.
If this occurs, the undervoltage monitors pull the GATE
