LTC4215/LTC4215-2
19
4215fe
APPLICATIONS INFORMATION
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS R/W ACK DATA ACK DATA ACK
1 - 7 8 9
4215 F06
a6 - a0 b7 - b0 b7 - b0
1 - 7 8 9 1 - 7 8 9
P
S
Figure 6. Data Transfer Over I
2
C or SMBus
Digital Interface
The LTC4215 communicates with a bus master using a
2-wire interface compatible with I
2
C Bus and SMBus, an
I
2
C extension for low power devices.
The LTC4215 is a read-write slave device and supports
SMBus bus Read Byte, Write Byte, Read Word and Write
Word commands. The second word in a Read Word com-
mand is identical to the fi rst word. The second word in a
Write Word command is ignored. Data formats for these
commands are shown in Figures 6 to 11.
START and STOP Conditions
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a start
condition by transitioning SDA from high to low while SCL
is high, as shown in Figure 6. When the master has fi nished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
I
2
C Device Addressing
Twenty-seven distinct bus addresses are available using
three 3-state address pins, ADR0-ADR2. Table 1 shows
the correspondence between pin states and addresses.
Note that address bits B7 and B6 are internally confi gured
to 10. In addition, the LTC4215 responds to two special
addresses. Address (1011 111) is a mass write address
that writes to all LTC4215s, regardless of their individual
address settings. Mass write can be disabled by setting
register A4 to zero. Address (0001 100) is the SMBus Alert
Response Address. If the LTC4215 is pulling low on the
ALERT pin, it acknowledges this address by broadcasting
its address and releasing the ALERT pin.
Acknowledge
The acknowledge signal is used in handshaking between
transmitter and receiver to indicate that the last byte of
data was received. The transmitter always releases the
SDA line during the acknowledge clock pulse. When the
slave is the receiver, it pulls down the SDA line so that it
remains LOW during this pulse to acknowledge receipt
of the data. If the slave fails to acknowledge by leaving
SDA high, then the master may abort the transmission by
generating a STOP condition. When the master is receiving
data from the slave, the master pulls down the SDA line
during the clock pulse to indicate receipt of the data. After
the last byte has been received the master leaves the SDA
line HIGH (not acknowledge) and issues a stop condition
to terminate the transmission.
Write Protocol
The master begins communication with a START con-
dition followed by the seven bit slave address and the
R/W bit set to zero, as shown in Figure 7. The addressed
LTC4215 acknowledges this and then the master sends
a command byte which indicates which internal register
the master wishes to write. The LTC4215 acknowledges
this and then latches the lower three bits of the command
byte into its internal Register Address pointer. The master
then delivers the data byte and the LTC4215 acknowledges
once more and latches the data into its control register.
